hw_error() calls exit(). This a bit overkill when we can log the accesses as unimplemented or guest error. When fuzzing the devices, we don't want the whole process to exit. Replace some hw_error() calls by qemu_log_mask(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200526094052.1723-3-f4bug@amsat.org> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
693 lines
18 KiB
C
693 lines
18 KiB
C
/*
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* ColdFire Fast Ethernet Controller emulation.
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*
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* Copyright (c) 2007 CodeSourcery.
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*
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* This code is licensed under the GPL
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/irq.h"
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#include "net/net.h"
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#include "qemu/module.h"
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#include "hw/m68k/mcf.h"
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#include "hw/m68k/mcf_fec.h"
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#include "hw/net/mii.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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/* For crc32 */
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#include <zlib.h>
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//#define DEBUG_FEC 1
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#ifdef DEBUG_FEC
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#define DPRINTF(fmt, ...) \
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do { printf("mcf_fec: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) do {} while(0)
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#endif
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#define FEC_MAX_DESC 1024
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#define FEC_MAX_FRAME_SIZE 2032
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#define FEC_MIB_SIZE 64
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typedef struct {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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qemu_irq irq[FEC_NUM_IRQ];
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NICState *nic;
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NICConf conf;
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uint32_t irq_state;
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uint32_t eir;
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uint32_t eimr;
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int rx_enabled;
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uint32_t rx_descriptor;
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uint32_t tx_descriptor;
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uint32_t ecr;
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uint32_t mmfr;
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uint32_t mscr;
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uint32_t rcr;
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uint32_t tcr;
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uint32_t tfwr;
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uint32_t rfsr;
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uint32_t erdsr;
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uint32_t etdsr;
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uint32_t emrbr;
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uint32_t mib[FEC_MIB_SIZE];
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} mcf_fec_state;
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#define FEC_INT_HB 0x80000000
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#define FEC_INT_BABR 0x40000000
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#define FEC_INT_BABT 0x20000000
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#define FEC_INT_GRA 0x10000000
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#define FEC_INT_TXF 0x08000000
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#define FEC_INT_TXB 0x04000000
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#define FEC_INT_RXF 0x02000000
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#define FEC_INT_RXB 0x01000000
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#define FEC_INT_MII 0x00800000
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#define FEC_INT_EB 0x00400000
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#define FEC_INT_LC 0x00200000
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#define FEC_INT_RL 0x00100000
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#define FEC_INT_UN 0x00080000
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#define FEC_EN 2
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#define FEC_RESET 1
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/* Map interrupt flags onto IRQ lines. */
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static const uint32_t mcf_fec_irq_map[FEC_NUM_IRQ] = {
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FEC_INT_TXF,
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FEC_INT_TXB,
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FEC_INT_UN,
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FEC_INT_RL,
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FEC_INT_RXF,
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FEC_INT_RXB,
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FEC_INT_MII,
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FEC_INT_LC,
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FEC_INT_HB,
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FEC_INT_GRA,
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FEC_INT_EB,
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FEC_INT_BABT,
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FEC_INT_BABR
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};
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/* Buffer Descriptor. */
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typedef struct {
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uint16_t flags;
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uint16_t length;
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uint32_t data;
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} mcf_fec_bd;
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#define FEC_BD_R 0x8000
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#define FEC_BD_E 0x8000
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#define FEC_BD_O1 0x4000
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#define FEC_BD_W 0x2000
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#define FEC_BD_O2 0x1000
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#define FEC_BD_L 0x0800
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#define FEC_BD_TC 0x0400
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#define FEC_BD_ABC 0x0200
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#define FEC_BD_M 0x0100
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#define FEC_BD_BC 0x0080
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#define FEC_BD_MC 0x0040
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#define FEC_BD_LG 0x0020
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#define FEC_BD_NO 0x0010
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#define FEC_BD_CR 0x0004
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#define FEC_BD_OV 0x0002
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#define FEC_BD_TR 0x0001
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#define MIB_RMON_T_DROP 0
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#define MIB_RMON_T_PACKETS 1
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#define MIB_RMON_T_BC_PKT 2
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#define MIB_RMON_T_MC_PKT 3
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#define MIB_RMON_T_CRC_ALIGN 4
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#define MIB_RMON_T_UNDERSIZE 5
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#define MIB_RMON_T_OVERSIZE 6
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#define MIB_RMON_T_FRAG 7
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#define MIB_RMON_T_JAB 8
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#define MIB_RMON_T_COL 9
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#define MIB_RMON_T_P64 10
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#define MIB_RMON_T_P65TO127 11
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#define MIB_RMON_T_P128TO255 12
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#define MIB_RMON_T_P256TO511 13
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#define MIB_RMON_T_P512TO1023 14
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#define MIB_RMON_T_P1024TO2047 15
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#define MIB_RMON_T_P_GTE2048 16
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#define MIB_RMON_T_OCTETS 17
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#define MIB_IEEE_T_DROP 18
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#define MIB_IEEE_T_FRAME_OK 19
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#define MIB_IEEE_T_1COL 20
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#define MIB_IEEE_T_MCOL 21
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#define MIB_IEEE_T_DEF 22
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#define MIB_IEEE_T_LCOL 23
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#define MIB_IEEE_T_EXCOL 24
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#define MIB_IEEE_T_MACERR 25
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#define MIB_IEEE_T_CSERR 26
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#define MIB_IEEE_T_SQE 27
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#define MIB_IEEE_T_FDXFC 28
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#define MIB_IEEE_T_OCTETS_OK 29
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#define MIB_RMON_R_DROP 32
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#define MIB_RMON_R_PACKETS 33
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#define MIB_RMON_R_BC_PKT 34
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#define MIB_RMON_R_MC_PKT 35
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#define MIB_RMON_R_CRC_ALIGN 36
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#define MIB_RMON_R_UNDERSIZE 37
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#define MIB_RMON_R_OVERSIZE 38
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#define MIB_RMON_R_FRAG 39
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#define MIB_RMON_R_JAB 40
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#define MIB_RMON_R_RESVD_0 41
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#define MIB_RMON_R_P64 42
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#define MIB_RMON_R_P65TO127 43
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#define MIB_RMON_R_P128TO255 44
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#define MIB_RMON_R_P256TO511 45
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#define MIB_RMON_R_P512TO1023 46
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#define MIB_RMON_R_P1024TO2047 47
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#define MIB_RMON_R_P_GTE2048 48
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#define MIB_RMON_R_OCTETS 49
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#define MIB_IEEE_R_DROP 50
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#define MIB_IEEE_R_FRAME_OK 51
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#define MIB_IEEE_R_CRC 52
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#define MIB_IEEE_R_ALIGN 53
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#define MIB_IEEE_R_MACERR 54
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#define MIB_IEEE_R_FDXFC 55
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#define MIB_IEEE_R_OCTETS_OK 56
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static void mcf_fec_read_bd(mcf_fec_bd *bd, uint32_t addr)
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{
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cpu_physical_memory_read(addr, bd, sizeof(*bd));
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be16_to_cpus(&bd->flags);
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be16_to_cpus(&bd->length);
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be32_to_cpus(&bd->data);
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}
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static void mcf_fec_write_bd(mcf_fec_bd *bd, uint32_t addr)
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{
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mcf_fec_bd tmp;
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tmp.flags = cpu_to_be16(bd->flags);
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tmp.length = cpu_to_be16(bd->length);
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tmp.data = cpu_to_be32(bd->data);
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cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
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}
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static void mcf_fec_update(mcf_fec_state *s)
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{
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uint32_t active;
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uint32_t changed;
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uint32_t mask;
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int i;
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active = s->eir & s->eimr;
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changed = active ^s->irq_state;
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for (i = 0; i < FEC_NUM_IRQ; i++) {
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mask = mcf_fec_irq_map[i];
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if (changed & mask) {
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DPRINTF("IRQ %d = %d\n", i, (active & mask) != 0);
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qemu_set_irq(s->irq[i], (active & mask) != 0);
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}
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}
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s->irq_state = active;
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}
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static void mcf_fec_tx_stats(mcf_fec_state *s, int size)
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{
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s->mib[MIB_RMON_T_PACKETS]++;
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s->mib[MIB_RMON_T_OCTETS] += size;
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if (size < 64) {
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s->mib[MIB_RMON_T_FRAG]++;
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} else if (size == 64) {
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s->mib[MIB_RMON_T_P64]++;
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} else if (size < 128) {
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s->mib[MIB_RMON_T_P65TO127]++;
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} else if (size < 256) {
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s->mib[MIB_RMON_T_P128TO255]++;
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} else if (size < 512) {
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s->mib[MIB_RMON_T_P256TO511]++;
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} else if (size < 1024) {
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s->mib[MIB_RMON_T_P512TO1023]++;
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} else if (size < 2048) {
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s->mib[MIB_RMON_T_P1024TO2047]++;
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} else {
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s->mib[MIB_RMON_T_P_GTE2048]++;
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}
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s->mib[MIB_IEEE_T_FRAME_OK]++;
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s->mib[MIB_IEEE_T_OCTETS_OK] += size;
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}
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static void mcf_fec_do_tx(mcf_fec_state *s)
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{
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uint32_t addr;
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mcf_fec_bd bd;
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int frame_size;
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int len, descnt = 0;
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uint8_t frame[FEC_MAX_FRAME_SIZE];
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uint8_t *ptr;
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DPRINTF("do_tx\n");
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ptr = frame;
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frame_size = 0;
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addr = s->tx_descriptor;
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while (descnt++ < FEC_MAX_DESC) {
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mcf_fec_read_bd(&bd, addr);
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DPRINTF("tx_bd %x flags %04x len %d data %08x\n",
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addr, bd.flags, bd.length, bd.data);
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if ((bd.flags & FEC_BD_R) == 0) {
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/* Run out of descriptors to transmit. */
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break;
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}
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len = bd.length;
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if (frame_size + len > FEC_MAX_FRAME_SIZE) {
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len = FEC_MAX_FRAME_SIZE - frame_size;
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s->eir |= FEC_INT_BABT;
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}
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cpu_physical_memory_read(bd.data, ptr, len);
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ptr += len;
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frame_size += len;
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if (bd.flags & FEC_BD_L) {
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/* Last buffer in frame. */
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DPRINTF("Sending packet\n");
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qemu_send_packet(qemu_get_queue(s->nic), frame, frame_size);
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mcf_fec_tx_stats(s, frame_size);
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ptr = frame;
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frame_size = 0;
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s->eir |= FEC_INT_TXF;
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}
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s->eir |= FEC_INT_TXB;
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bd.flags &= ~FEC_BD_R;
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/* Write back the modified descriptor. */
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mcf_fec_write_bd(&bd, addr);
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/* Advance to the next descriptor. */
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if ((bd.flags & FEC_BD_W) != 0) {
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addr = s->etdsr;
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} else {
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addr += 8;
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}
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}
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s->tx_descriptor = addr;
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}
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static void mcf_fec_enable_rx(mcf_fec_state *s)
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{
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NetClientState *nc = qemu_get_queue(s->nic);
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mcf_fec_bd bd;
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mcf_fec_read_bd(&bd, s->rx_descriptor);
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s->rx_enabled = ((bd.flags & FEC_BD_E) != 0);
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if (s->rx_enabled) {
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qemu_flush_queued_packets(nc);
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}
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}
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static void mcf_fec_reset(DeviceState *dev)
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{
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mcf_fec_state *s = MCF_FEC_NET(dev);
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s->eir = 0;
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s->eimr = 0;
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s->rx_enabled = 0;
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s->ecr = 0;
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s->mscr = 0;
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s->rcr = 0x05ee0001;
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s->tcr = 0;
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s->tfwr = 0;
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s->rfsr = 0x500;
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}
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#define MMFR_WRITE_OP (1 << 28)
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#define MMFR_READ_OP (2 << 28)
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#define MMFR_PHYADDR(v) (((v) >> 23) & 0x1f)
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#define MMFR_REGNUM(v) (((v) >> 18) & 0x1f)
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static uint64_t mcf_fec_read_mdio(mcf_fec_state *s)
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{
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uint64_t v;
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if (s->mmfr & MMFR_WRITE_OP)
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return s->mmfr;
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if (MMFR_PHYADDR(s->mmfr) != 1)
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return s->mmfr |= 0xffff;
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switch (MMFR_REGNUM(s->mmfr)) {
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case MII_BMCR:
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v = MII_BMCR_SPEED | MII_BMCR_AUTOEN | MII_BMCR_FD;
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break;
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case MII_BMSR:
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v = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD |
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MII_BMSR_10T_HD | MII_BMSR_MFPS | MII_BMSR_AN_COMP |
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MII_BMSR_AUTONEG | MII_BMSR_LINK_ST;
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break;
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case MII_PHYID1:
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v = DP83848_PHYID1;
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break;
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case MII_PHYID2:
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v = DP83848_PHYID2;
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break;
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case MII_ANAR:
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v = MII_ANAR_TXFD | MII_ANAR_TX | MII_ANAR_10FD |
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MII_ANAR_10 | MII_ANAR_CSMACD;
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break;
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case MII_ANLPAR:
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v = MII_ANLPAR_ACK | MII_ANLPAR_TXFD | MII_ANLPAR_TX |
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MII_ANLPAR_10FD | MII_ANLPAR_10 | MII_ANLPAR_CSMACD;
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break;
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default:
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v = 0xffff;
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break;
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}
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s->mmfr = (s->mmfr & ~0xffff) | v;
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return s->mmfr;
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}
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static uint64_t mcf_fec_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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mcf_fec_state *s = (mcf_fec_state *)opaque;
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switch (addr & 0x3ff) {
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case 0x004: return s->eir;
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case 0x008: return s->eimr;
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case 0x010: return s->rx_enabled ? (1 << 24) : 0; /* RDAR */
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case 0x014: return 0; /* TDAR */
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case 0x024: return s->ecr;
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case 0x040: return mcf_fec_read_mdio(s);
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case 0x044: return s->mscr;
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case 0x064: return 0; /* MIBC */
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case 0x084: return s->rcr;
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case 0x0c4: return s->tcr;
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case 0x0e4: /* PALR */
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return (s->conf.macaddr.a[0] << 24) | (s->conf.macaddr.a[1] << 16)
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| (s->conf.macaddr.a[2] << 8) | s->conf.macaddr.a[3];
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break;
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case 0x0e8: /* PAUR */
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return (s->conf.macaddr.a[4] << 24) | (s->conf.macaddr.a[5] << 16) | 0x8808;
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case 0x0ec: return 0x10000; /* OPD */
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case 0x118: return 0;
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case 0x11c: return 0;
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case 0x120: return 0;
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case 0x124: return 0;
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case 0x144: return s->tfwr;
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case 0x14c: return 0x600;
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case 0x150: return s->rfsr;
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case 0x180: return s->erdsr;
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case 0x184: return s->etdsr;
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case 0x188: return s->emrbr;
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case 0x200 ... 0x2e0: return s->mib[(addr & 0x1ff) / 4];
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%" HWADDR_PRIX "\n",
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__func__, addr);
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return 0;
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}
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}
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static void mcf_fec_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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mcf_fec_state *s = (mcf_fec_state *)opaque;
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switch (addr & 0x3ff) {
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case 0x004:
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s->eir &= ~value;
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break;
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case 0x008:
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s->eimr = value;
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break;
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case 0x010: /* RDAR */
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if ((s->ecr & FEC_EN) && !s->rx_enabled) {
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DPRINTF("RX enable\n");
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mcf_fec_enable_rx(s);
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}
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break;
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case 0x014: /* TDAR */
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if (s->ecr & FEC_EN) {
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mcf_fec_do_tx(s);
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}
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break;
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case 0x024:
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s->ecr = value;
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if (value & FEC_RESET) {
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DPRINTF("Reset\n");
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mcf_fec_reset(opaque);
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}
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if ((s->ecr & FEC_EN) == 0) {
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s->rx_enabled = 0;
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}
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break;
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case 0x040:
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s->mmfr = value;
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s->eir |= FEC_INT_MII;
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break;
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case 0x044:
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s->mscr = value & 0xfe;
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break;
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case 0x064:
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/* TODO: Implement MIB. */
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break;
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case 0x084:
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s->rcr = value & 0x07ff003f;
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/* TODO: Implement LOOP mode. */
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break;
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case 0x0c4: /* TCR */
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/* We transmit immediately, so raise GRA immediately. */
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s->tcr = value;
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if (value & 1)
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s->eir |= FEC_INT_GRA;
|
|
break;
|
|
case 0x0e4: /* PALR */
|
|
s->conf.macaddr.a[0] = value >> 24;
|
|
s->conf.macaddr.a[1] = value >> 16;
|
|
s->conf.macaddr.a[2] = value >> 8;
|
|
s->conf.macaddr.a[3] = value;
|
|
break;
|
|
case 0x0e8: /* PAUR */
|
|
s->conf.macaddr.a[4] = value >> 24;
|
|
s->conf.macaddr.a[5] = value >> 16;
|
|
break;
|
|
case 0x0ec:
|
|
/* OPD */
|
|
break;
|
|
case 0x118:
|
|
case 0x11c:
|
|
case 0x120:
|
|
case 0x124:
|
|
/* TODO: implement MAC hash filtering. */
|
|
break;
|
|
case 0x144:
|
|
s->tfwr = value & 3;
|
|
break;
|
|
case 0x14c:
|
|
/* FRBR writes ignored. */
|
|
break;
|
|
case 0x150:
|
|
s->rfsr = (value & 0x3fc) | 0x400;
|
|
break;
|
|
case 0x180:
|
|
s->erdsr = value & ~3;
|
|
s->rx_descriptor = s->erdsr;
|
|
break;
|
|
case 0x184:
|
|
s->etdsr = value & ~3;
|
|
s->tx_descriptor = s->etdsr;
|
|
break;
|
|
case 0x188:
|
|
s->emrbr = value > 0 ? value & 0x7F0 : 0x7F0;
|
|
break;
|
|
case 0x200 ... 0x2e0:
|
|
s->mib[(addr & 0x1ff) / 4] = value;
|
|
break;
|
|
default:
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%" HWADDR_PRIX "\n",
|
|
__func__, addr);
|
|
return;
|
|
}
|
|
mcf_fec_update(s);
|
|
}
|
|
|
|
static void mcf_fec_rx_stats(mcf_fec_state *s, int size)
|
|
{
|
|
s->mib[MIB_RMON_R_PACKETS]++;
|
|
s->mib[MIB_RMON_R_OCTETS] += size;
|
|
if (size < 64) {
|
|
s->mib[MIB_RMON_R_FRAG]++;
|
|
} else if (size == 64) {
|
|
s->mib[MIB_RMON_R_P64]++;
|
|
} else if (size < 128) {
|
|
s->mib[MIB_RMON_R_P65TO127]++;
|
|
} else if (size < 256) {
|
|
s->mib[MIB_RMON_R_P128TO255]++;
|
|
} else if (size < 512) {
|
|
s->mib[MIB_RMON_R_P256TO511]++;
|
|
} else if (size < 1024) {
|
|
s->mib[MIB_RMON_R_P512TO1023]++;
|
|
} else if (size < 2048) {
|
|
s->mib[MIB_RMON_R_P1024TO2047]++;
|
|
} else {
|
|
s->mib[MIB_RMON_R_P_GTE2048]++;
|
|
}
|
|
s->mib[MIB_IEEE_R_FRAME_OK]++;
|
|
s->mib[MIB_IEEE_R_OCTETS_OK] += size;
|
|
}
|
|
|
|
static int mcf_fec_have_receive_space(mcf_fec_state *s, size_t want)
|
|
{
|
|
mcf_fec_bd bd;
|
|
uint32_t addr;
|
|
|
|
/* Walk descriptor list to determine if we have enough buffer */
|
|
addr = s->rx_descriptor;
|
|
while (want > 0) {
|
|
mcf_fec_read_bd(&bd, addr);
|
|
if ((bd.flags & FEC_BD_E) == 0) {
|
|
return 0;
|
|
}
|
|
if (want < s->emrbr) {
|
|
return 1;
|
|
}
|
|
want -= s->emrbr;
|
|
/* Advance to the next descriptor. */
|
|
if ((bd.flags & FEC_BD_W) != 0) {
|
|
addr = s->erdsr;
|
|
} else {
|
|
addr += 8;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static ssize_t mcf_fec_receive(NetClientState *nc, const uint8_t *buf, size_t size)
|
|
{
|
|
mcf_fec_state *s = qemu_get_nic_opaque(nc);
|
|
mcf_fec_bd bd;
|
|
uint32_t flags = 0;
|
|
uint32_t addr;
|
|
uint32_t crc;
|
|
uint32_t buf_addr;
|
|
uint8_t *crc_ptr;
|
|
unsigned int buf_len;
|
|
size_t retsize;
|
|
|
|
DPRINTF("do_rx len %d\n", size);
|
|
if (!s->rx_enabled) {
|
|
return -1;
|
|
}
|
|
/* 4 bytes for the CRC. */
|
|
size += 4;
|
|
crc = cpu_to_be32(crc32(~0, buf, size));
|
|
crc_ptr = (uint8_t *)&crc;
|
|
/* Huge frames are truncted. */
|
|
if (size > FEC_MAX_FRAME_SIZE) {
|
|
size = FEC_MAX_FRAME_SIZE;
|
|
flags |= FEC_BD_TR | FEC_BD_LG;
|
|
}
|
|
/* Frames larger than the user limit just set error flags. */
|
|
if (size > (s->rcr >> 16)) {
|
|
flags |= FEC_BD_LG;
|
|
}
|
|
/* Check if we have enough space in current descriptors */
|
|
if (!mcf_fec_have_receive_space(s, size)) {
|
|
return 0;
|
|
}
|
|
addr = s->rx_descriptor;
|
|
retsize = size;
|
|
while (size > 0) {
|
|
mcf_fec_read_bd(&bd, addr);
|
|
buf_len = (size <= s->emrbr) ? size: s->emrbr;
|
|
bd.length = buf_len;
|
|
size -= buf_len;
|
|
DPRINTF("rx_bd %x length %d\n", addr, bd.length);
|
|
/* The last 4 bytes are the CRC. */
|
|
if (size < 4)
|
|
buf_len += size - 4;
|
|
buf_addr = bd.data;
|
|
cpu_physical_memory_write(buf_addr, buf, buf_len);
|
|
buf += buf_len;
|
|
if (size < 4) {
|
|
cpu_physical_memory_write(buf_addr + buf_len, crc_ptr, 4 - size);
|
|
crc_ptr += 4 - size;
|
|
}
|
|
bd.flags &= ~FEC_BD_E;
|
|
if (size == 0) {
|
|
/* Last buffer in frame. */
|
|
bd.flags |= flags | FEC_BD_L;
|
|
DPRINTF("rx frame flags %04x\n", bd.flags);
|
|
s->eir |= FEC_INT_RXF;
|
|
} else {
|
|
s->eir |= FEC_INT_RXB;
|
|
}
|
|
mcf_fec_write_bd(&bd, addr);
|
|
/* Advance to the next descriptor. */
|
|
if ((bd.flags & FEC_BD_W) != 0) {
|
|
addr = s->erdsr;
|
|
} else {
|
|
addr += 8;
|
|
}
|
|
}
|
|
s->rx_descriptor = addr;
|
|
mcf_fec_rx_stats(s, retsize);
|
|
mcf_fec_enable_rx(s);
|
|
mcf_fec_update(s);
|
|
return retsize;
|
|
}
|
|
|
|
static const MemoryRegionOps mcf_fec_ops = {
|
|
.read = mcf_fec_read,
|
|
.write = mcf_fec_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static NetClientInfo net_mcf_fec_info = {
|
|
.type = NET_CLIENT_DRIVER_NIC,
|
|
.size = sizeof(NICState),
|
|
.receive = mcf_fec_receive,
|
|
};
|
|
|
|
static void mcf_fec_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
mcf_fec_state *s = MCF_FEC_NET(dev);
|
|
|
|
s->nic = qemu_new_nic(&net_mcf_fec_info, &s->conf,
|
|
object_get_typename(OBJECT(dev)), dev->id, s);
|
|
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
|
|
}
|
|
|
|
static void mcf_fec_instance_init(Object *obj)
|
|
{
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
|
mcf_fec_state *s = MCF_FEC_NET(obj);
|
|
int i;
|
|
|
|
memory_region_init_io(&s->iomem, obj, &mcf_fec_ops, s, "fec", 0x400);
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
|
for (i = 0; i < FEC_NUM_IRQ; i++) {
|
|
sysbus_init_irq(sbd, &s->irq[i]);
|
|
}
|
|
}
|
|
|
|
static Property mcf_fec_properties[] = {
|
|
DEFINE_NIC_PROPERTIES(mcf_fec_state, conf),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void mcf_fec_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
|
|
dc->realize = mcf_fec_realize;
|
|
dc->desc = "MCF Fast Ethernet Controller network device";
|
|
dc->reset = mcf_fec_reset;
|
|
device_class_set_props(dc, mcf_fec_properties);
|
|
}
|
|
|
|
static const TypeInfo mcf_fec_info = {
|
|
.name = TYPE_MCF_FEC_NET,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(mcf_fec_state),
|
|
.instance_init = mcf_fec_instance_init,
|
|
.class_init = mcf_fec_class_init,
|
|
};
|
|
|
|
static void mcf_fec_register_types(void)
|
|
{
|
|
type_register_static(&mcf_fec_info);
|
|
}
|
|
|
|
type_init(mcf_fec_register_types)
|