Note: the "Platform Reset Attack Mitigation" specification isn't explicit about NVDIMM, since they could have different usages. It uses the term "system memory" generally (and also "volatile memory RAM" in its introduction). For initial support, I propose to consider non-volatile memory as not being subject to the memory clear. There is an on-going discussion in the TCG "pcclientwg" working group for future revisions. CPU cache clearing is done unconditionally in edk2 since commit d20ae95a13e851 (edk2-stable201811). Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Tested-by: Stefan Berger <stefanb@linux.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
344 lines
9.6 KiB
C
344 lines
9.6 KiB
C
/*
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* tpm_crb.c - QEMU's TPM CRB interface emulator
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*
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* Copyright (c) 2018 Red Hat, Inc.
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*
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* Authors:
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* Marc-André Lureau <marcandre.lureau@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* tpm_crb is a device for TPM 2.0 Command Response Buffer (CRB) Interface
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* as defined in TCG PC Client Platform TPM Profile (PTP) Specification
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* Family “2.0” Level 00 Revision 01.03 v22
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "qapi/error.h"
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#include "exec/address-spaces.h"
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#include "hw/qdev-core.h"
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#include "hw/qdev-properties.h"
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#include "hw/pci/pci_ids.h"
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#include "hw/acpi/tpm.h"
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#include "migration/vmstate.h"
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#include "sysemu/tpm_backend.h"
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#include "sysemu/reset.h"
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#include "tpm_int.h"
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#include "tpm_util.h"
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#include "tpm_ppi.h"
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#include "trace.h"
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typedef struct CRBState {
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DeviceState parent_obj;
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TPMBackend *tpmbe;
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TPMBackendCmd cmd;
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uint32_t regs[TPM_CRB_R_MAX];
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MemoryRegion mmio;
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MemoryRegion cmdmem;
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size_t be_buffer_size;
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bool ppi_enabled;
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TPMPPI ppi;
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} CRBState;
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#define CRB(obj) OBJECT_CHECK(CRBState, (obj), TYPE_TPM_CRB)
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#define CRB_INTF_TYPE_CRB_ACTIVE 0b1
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#define CRB_INTF_VERSION_CRB 0b1
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#define CRB_INTF_CAP_LOCALITY_0_ONLY 0b0
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#define CRB_INTF_CAP_IDLE_FAST 0b0
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#define CRB_INTF_CAP_XFER_SIZE_64 0b11
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#define CRB_INTF_CAP_FIFO_NOT_SUPPORTED 0b0
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#define CRB_INTF_CAP_CRB_SUPPORTED 0b1
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#define CRB_INTF_IF_SELECTOR_CRB 0b1
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#define CRB_CTRL_CMD_SIZE (TPM_CRB_ADDR_SIZE - A_CRB_DATA_BUFFER)
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enum crb_loc_ctrl {
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CRB_LOC_CTRL_REQUEST_ACCESS = BIT(0),
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CRB_LOC_CTRL_RELINQUISH = BIT(1),
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CRB_LOC_CTRL_SEIZE = BIT(2),
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CRB_LOC_CTRL_RESET_ESTABLISHMENT_BIT = BIT(3),
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};
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enum crb_ctrl_req {
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CRB_CTRL_REQ_CMD_READY = BIT(0),
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CRB_CTRL_REQ_GO_IDLE = BIT(1),
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};
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enum crb_start {
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CRB_START_INVOKE = BIT(0),
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};
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enum crb_cancel {
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CRB_CANCEL_INVOKE = BIT(0),
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};
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#define TPM_CRB_NO_LOCALITY 0xff
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static uint64_t tpm_crb_mmio_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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CRBState *s = CRB(opaque);
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void *regs = (void *)&s->regs + (addr & ~3);
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unsigned offset = addr & 3;
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uint32_t val = *(uint32_t *)regs >> (8 * offset);
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switch (addr) {
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case A_CRB_LOC_STATE:
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val |= !tpm_backend_get_tpm_established_flag(s->tpmbe);
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break;
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}
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trace_tpm_crb_mmio_read(addr, size, val);
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return val;
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}
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static uint8_t tpm_crb_get_active_locty(CRBState *s)
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{
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if (!ARRAY_FIELD_EX32(s->regs, CRB_LOC_STATE, locAssigned)) {
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return TPM_CRB_NO_LOCALITY;
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}
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return ARRAY_FIELD_EX32(s->regs, CRB_LOC_STATE, activeLocality);
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}
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static void tpm_crb_mmio_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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CRBState *s = CRB(opaque);
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uint8_t locty = addr >> 12;
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trace_tpm_crb_mmio_write(addr, size, val);
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switch (addr) {
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case A_CRB_CTRL_REQ:
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switch (val) {
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case CRB_CTRL_REQ_CMD_READY:
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ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS,
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tpmIdle, 0);
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break;
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case CRB_CTRL_REQ_GO_IDLE:
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ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS,
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tpmIdle, 1);
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break;
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}
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break;
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case A_CRB_CTRL_CANCEL:
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if (val == CRB_CANCEL_INVOKE &&
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s->regs[R_CRB_CTRL_START] & CRB_START_INVOKE) {
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tpm_backend_cancel_cmd(s->tpmbe);
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}
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break;
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case A_CRB_CTRL_START:
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if (val == CRB_START_INVOKE &&
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!(s->regs[R_CRB_CTRL_START] & CRB_START_INVOKE) &&
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tpm_crb_get_active_locty(s) == locty) {
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void *mem = memory_region_get_ram_ptr(&s->cmdmem);
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s->regs[R_CRB_CTRL_START] |= CRB_START_INVOKE;
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s->cmd = (TPMBackendCmd) {
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.in = mem,
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.in_len = MIN(tpm_cmd_get_size(mem), s->be_buffer_size),
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.out = mem,
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.out_len = s->be_buffer_size,
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};
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tpm_backend_deliver_request(s->tpmbe, &s->cmd);
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}
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break;
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case A_CRB_LOC_CTRL:
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switch (val) {
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case CRB_LOC_CTRL_RESET_ESTABLISHMENT_BIT:
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/* not loc 3 or 4 */
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break;
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case CRB_LOC_CTRL_RELINQUISH:
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ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE,
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locAssigned, 0);
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ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS,
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Granted, 0);
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break;
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case CRB_LOC_CTRL_REQUEST_ACCESS:
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ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS,
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Granted, 1);
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ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS,
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beenSeized, 0);
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ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE,
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locAssigned, 1);
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break;
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}
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break;
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}
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}
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static const MemoryRegionOps tpm_crb_memory_ops = {
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.read = tpm_crb_mmio_read,
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.write = tpm_crb_mmio_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 4,
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},
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};
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static void tpm_crb_request_completed(TPMIf *ti, int ret)
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{
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CRBState *s = CRB(ti);
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s->regs[R_CRB_CTRL_START] &= ~CRB_START_INVOKE;
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if (ret != 0) {
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ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS,
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tpmSts, 1); /* fatal error */
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}
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}
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static enum TPMVersion tpm_crb_get_version(TPMIf *ti)
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{
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CRBState *s = CRB(ti);
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return tpm_backend_get_tpm_version(s->tpmbe);
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}
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static int tpm_crb_pre_save(void *opaque)
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{
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CRBState *s = opaque;
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tpm_backend_finish_sync(s->tpmbe);
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return 0;
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}
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static const VMStateDescription vmstate_tpm_crb = {
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.name = "tpm-crb",
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.pre_save = tpm_crb_pre_save,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, CRBState, TPM_CRB_R_MAX),
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VMSTATE_END_OF_LIST(),
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}
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};
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static Property tpm_crb_properties[] = {
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DEFINE_PROP_TPMBE("tpmdev", CRBState, tpmbe),
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DEFINE_PROP_BOOL("ppi", CRBState, ppi_enabled, true),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void tpm_crb_reset(void *dev)
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{
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CRBState *s = CRB(dev);
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if (s->ppi_enabled) {
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tpm_ppi_reset(&s->ppi);
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}
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tpm_backend_reset(s->tpmbe);
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memset(s->regs, 0, sizeof(s->regs));
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ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE,
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tpmRegValidSts, 1);
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ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS,
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tpmIdle, 1);
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ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID,
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InterfaceType, CRB_INTF_TYPE_CRB_ACTIVE);
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ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID,
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InterfaceVersion, CRB_INTF_VERSION_CRB);
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ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID,
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CapLocality, CRB_INTF_CAP_LOCALITY_0_ONLY);
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ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID,
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CapCRBIdleBypass, CRB_INTF_CAP_IDLE_FAST);
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ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID,
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CapDataXferSizeSupport, CRB_INTF_CAP_XFER_SIZE_64);
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ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID,
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CapFIFO, CRB_INTF_CAP_FIFO_NOT_SUPPORTED);
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ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID,
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CapCRB, CRB_INTF_CAP_CRB_SUPPORTED);
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ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID,
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InterfaceSelector, CRB_INTF_IF_SELECTOR_CRB);
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ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID,
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RID, 0b0000);
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ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID2,
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VID, PCI_VENDOR_ID_IBM);
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s->regs[R_CRB_CTRL_CMD_SIZE] = CRB_CTRL_CMD_SIZE;
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s->regs[R_CRB_CTRL_CMD_LADDR] = TPM_CRB_ADDR_BASE + A_CRB_DATA_BUFFER;
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s->regs[R_CRB_CTRL_RSP_SIZE] = CRB_CTRL_CMD_SIZE;
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s->regs[R_CRB_CTRL_RSP_ADDR] = TPM_CRB_ADDR_BASE + A_CRB_DATA_BUFFER;
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s->be_buffer_size = MIN(tpm_backend_get_buffer_size(s->tpmbe),
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CRB_CTRL_CMD_SIZE);
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tpm_backend_startup_tpm(s->tpmbe, s->be_buffer_size);
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}
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static void tpm_crb_realize(DeviceState *dev, Error **errp)
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{
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CRBState *s = CRB(dev);
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if (!tpm_find()) {
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error_setg(errp, "at most one TPM device is permitted");
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return;
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}
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if (!s->tpmbe) {
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error_setg(errp, "'tpmdev' property is required");
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return;
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}
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memory_region_init_io(&s->mmio, OBJECT(s), &tpm_crb_memory_ops, s,
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"tpm-crb-mmio", sizeof(s->regs));
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memory_region_init_ram(&s->cmdmem, OBJECT(s),
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"tpm-crb-cmd", CRB_CTRL_CMD_SIZE, errp);
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memory_region_add_subregion(get_system_memory(),
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TPM_CRB_ADDR_BASE, &s->mmio);
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memory_region_add_subregion(get_system_memory(),
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TPM_CRB_ADDR_BASE + sizeof(s->regs), &s->cmdmem);
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if (s->ppi_enabled) {
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tpm_ppi_init(&s->ppi, get_system_memory(),
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TPM_PPI_ADDR_BASE, OBJECT(s));
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}
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qemu_register_reset(tpm_crb_reset, dev);
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}
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static void tpm_crb_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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TPMIfClass *tc = TPM_IF_CLASS(klass);
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dc->realize = tpm_crb_realize;
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dc->props = tpm_crb_properties;
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dc->vmsd = &vmstate_tpm_crb;
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dc->user_creatable = true;
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tc->model = TPM_MODEL_TPM_CRB;
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tc->get_version = tpm_crb_get_version;
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tc->request_completed = tpm_crb_request_completed;
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set_bit(DEVICE_CATEGORY_MISC, dc->categories);
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}
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static const TypeInfo tpm_crb_info = {
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.name = TYPE_TPM_CRB,
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/* could be TYPE_SYS_BUS_DEVICE (or LPC etc) */
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(CRBState),
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.class_init = tpm_crb_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ TYPE_TPM_IF },
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{ }
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}
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};
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static void tpm_crb_register(void)
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{
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type_register_static(&tpm_crb_info);
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}
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type_init(tpm_crb_register)
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