git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@863 c046a42c-6fe2-441c-8c8c-71466251a162
1083 lines
30 KiB
C
1083 lines
30 KiB
C
/*
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* QEMU PCI bus manager
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*
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* Copyright (c) 2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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//#define DEBUG_PCI
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#define PCI_VENDOR_ID 0x00 /* 16 bits */
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#define PCI_DEVICE_ID 0x02 /* 16 bits */
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#define PCI_COMMAND 0x04 /* 16 bits */
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#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
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#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
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#define PCI_CLASS_DEVICE 0x0a /* Device class */
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#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
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#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
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#define PCI_MIN_GNT 0x3e /* 8 bits */
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#define PCI_MAX_LAT 0x3f /* 8 bits */
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/* just used for simpler irq handling. */
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#define PCI_DEVICES_MAX 64
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#define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32)
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typedef struct PCIBridge {
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uint32_t config_reg;
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PCIDevice **pci_bus[256];
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} PCIBridge;
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static PCIBridge pci_bridge;
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target_phys_addr_t pci_mem_base;
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static int pci_irq_index;
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static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS];
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/* -1 for devfn means auto assign */
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PCIDevice *pci_register_device(const char *name, int instance_size,
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int bus_num, int devfn,
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PCIConfigReadFunc *config_read,
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PCIConfigWriteFunc *config_write)
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{
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PCIBridge *s = &pci_bridge;
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PCIDevice *pci_dev, **bus;
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if (pci_irq_index >= PCI_DEVICES_MAX)
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return NULL;
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if (!s->pci_bus[bus_num]) {
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s->pci_bus[bus_num] = qemu_mallocz(256 * sizeof(PCIDevice *));
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if (!s->pci_bus[bus_num])
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return NULL;
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}
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bus = s->pci_bus[bus_num];
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if (devfn < 0) {
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for(devfn = 0 ; devfn < 256; devfn += 8) {
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if (!bus[devfn])
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goto found;
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}
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return NULL;
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found: ;
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}
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pci_dev = qemu_mallocz(instance_size);
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if (!pci_dev)
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return NULL;
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pci_dev->bus_num = bus_num;
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pci_dev->devfn = devfn;
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pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
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if (!config_read)
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config_read = pci_default_read_config;
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if (!config_write)
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config_write = pci_default_write_config;
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pci_dev->config_read = config_read;
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pci_dev->config_write = config_write;
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pci_dev->irq_index = pci_irq_index++;
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bus[devfn] = pci_dev;
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return pci_dev;
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}
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void pci_register_io_region(PCIDevice *pci_dev, int region_num,
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uint32_t size, int type,
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PCIMapIORegionFunc *map_func)
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{
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PCIIORegion *r;
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if ((unsigned int)region_num >= 6)
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return;
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r = &pci_dev->io_regions[region_num];
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r->addr = -1;
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r->size = size;
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r->type = type;
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r->map_func = map_func;
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}
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static void pci_addr_writel(void* opaque, uint32_t addr, uint32_t val)
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{
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PCIBridge *s = opaque;
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s->config_reg = val;
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}
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static uint32_t pci_addr_readl(void* opaque, uint32_t addr)
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{
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PCIBridge *s = opaque;
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return s->config_reg;
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}
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static void pci_update_mappings(PCIDevice *d)
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{
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PCIIORegion *r;
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int cmd, i;
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uint32_t last_addr, new_addr;
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cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
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for(i = 0; i < 6; i++) {
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r = &d->io_regions[i];
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if (r->size != 0) {
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if (r->type & PCI_ADDRESS_SPACE_IO) {
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if (cmd & PCI_COMMAND_IO) {
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new_addr = le32_to_cpu(*(uint32_t *)(d->config +
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0x10 + i * 4));
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new_addr = new_addr & ~(r->size - 1);
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last_addr = new_addr + r->size - 1;
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/* NOTE: we have only 64K ioports on PC */
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if (last_addr <= new_addr || new_addr == 0 ||
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last_addr >= 0x10000) {
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new_addr = -1;
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}
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} else {
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new_addr = -1;
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}
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} else {
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if (cmd & PCI_COMMAND_MEMORY) {
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new_addr = le32_to_cpu(*(uint32_t *)(d->config +
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0x10 + i * 4));
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new_addr = new_addr & ~(r->size - 1);
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last_addr = new_addr + r->size - 1;
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/* NOTE: we do not support wrapping */
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/* XXX: as we cannot support really dynamic
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mappings, we handle specific values as invalid
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mappings. */
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if (last_addr <= new_addr || new_addr == 0 ||
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last_addr == -1) {
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new_addr = -1;
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}
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} else {
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new_addr = -1;
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}
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}
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/* now do the real mapping */
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if (new_addr != r->addr) {
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if (r->addr != -1) {
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if (r->type & PCI_ADDRESS_SPACE_IO) {
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int class;
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/* NOTE: specific hack for IDE in PC case:
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only one byte must be mapped. */
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class = d->config[0x0a] | (d->config[0x0b] << 8);
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if (class == 0x0101 && r->size == 4) {
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isa_unassign_ioport(r->addr + 2, 1);
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} else {
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isa_unassign_ioport(r->addr, r->size);
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}
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} else {
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cpu_register_physical_memory(r->addr + pci_mem_base,
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r->size,
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IO_MEM_UNASSIGNED);
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}
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}
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r->addr = new_addr;
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if (r->addr != -1) {
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r->map_func(d, i, r->addr, r->size, r->type);
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}
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}
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}
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}
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}
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uint32_t pci_default_read_config(PCIDevice *d,
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uint32_t address, int len)
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{
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uint32_t val;
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switch(len) {
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case 1:
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val = d->config[address];
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break;
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case 2:
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val = le16_to_cpu(*(uint16_t *)(d->config + address));
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break;
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default:
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case 4:
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val = le32_to_cpu(*(uint32_t *)(d->config + address));
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break;
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}
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return val;
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}
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void pci_default_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{
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int can_write, i;
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uint32_t end, addr;
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if (len == 4 && (address >= 0x10 && address < 0x10 + 4 * 6)) {
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PCIIORegion *r;
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int reg;
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reg = (address - 0x10) >> 2;
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r = &d->io_regions[reg];
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if (r->size == 0)
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goto default_config;
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/* compute the stored value */
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val &= ~(r->size - 1);
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val |= r->type;
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*(uint32_t *)(d->config + 0x10 + reg * 4) = cpu_to_le32(val);
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pci_update_mappings(d);
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return;
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}
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default_config:
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/* not efficient, but simple */
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addr = address;
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for(i = 0; i < len; i++) {
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/* default read/write accesses */
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switch(addr) {
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case 0x00:
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case 0x01:
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case 0x02:
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case 0x03:
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case 0x08:
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case 0x09:
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case 0x0a:
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case 0x0b:
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case 0x0e:
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case 0x3d:
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can_write = 0;
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break;
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default:
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can_write = 1;
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break;
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}
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if (can_write) {
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d->config[addr] = val;
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}
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addr++;
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val >>= 8;
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}
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end = address + len;
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if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
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/* if the command register is modified, we must modify the mappings */
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pci_update_mappings(d);
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}
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}
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static void pci_data_write(void *opaque, uint32_t addr,
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uint32_t val, int len)
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{
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PCIBridge *s = opaque;
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PCIDevice **bus, *pci_dev;
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int config_addr;
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#if defined(DEBUG_PCI) && 0
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printf("pci_data_write: addr=%08x val=%08x len=%d\n",
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s->config_reg, val, len);
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#endif
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if (!(s->config_reg & (1 << 31))) {
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return;
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}
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if ((s->config_reg & 0x3) != 0) {
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return;
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}
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bus = s->pci_bus[(s->config_reg >> 16) & 0xff];
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if (!bus)
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return;
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pci_dev = bus[(s->config_reg >> 8) & 0xff];
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if (!pci_dev)
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return;
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config_addr = (s->config_reg & 0xfc) | (addr & 3);
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#if defined(DEBUG_PCI)
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printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
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pci_dev->name, config_addr, val, len);
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#endif
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pci_dev->config_write(pci_dev, config_addr, val, len);
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}
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static uint32_t pci_data_read(void *opaque, uint32_t addr,
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int len)
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{
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PCIBridge *s = opaque;
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PCIDevice **bus, *pci_dev;
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int config_addr;
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uint32_t val;
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if (!(s->config_reg & (1 << 31)))
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goto fail;
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if ((s->config_reg & 0x3) != 0)
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goto fail;
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bus = s->pci_bus[(s->config_reg >> 16) & 0xff];
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if (!bus)
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goto fail;
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pci_dev = bus[(s->config_reg >> 8) & 0xff];
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if (!pci_dev) {
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fail:
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switch(len) {
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case 1:
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val = 0xff;
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break;
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case 2:
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val = 0xffff;
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break;
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default:
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case 4:
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val = 0xffffffff;
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break;
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}
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goto the_end;
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}
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config_addr = (s->config_reg & 0xfc) | (addr & 3);
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val = pci_dev->config_read(pci_dev, config_addr, len);
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#if defined(DEBUG_PCI)
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printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
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pci_dev->name, config_addr, val, len);
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#endif
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the_end:
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#if defined(DEBUG_PCI) && 0
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printf("pci_data_read: addr=%08x val=%08x len=%d\n",
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s->config_reg, val, len);
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#endif
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return val;
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}
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static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val)
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{
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pci_data_write(opaque, addr, val, 1);
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}
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static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val)
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{
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pci_data_write(opaque, addr, val, 2);
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}
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static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val)
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{
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pci_data_write(opaque, addr, val, 4);
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}
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static uint32_t pci_data_readb(void* opaque, uint32_t addr)
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{
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return pci_data_read(opaque, addr, 1);
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}
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static uint32_t pci_data_readw(void* opaque, uint32_t addr)
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{
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return pci_data_read(opaque, addr, 2);
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}
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static uint32_t pci_data_readl(void* opaque, uint32_t addr)
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{
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return pci_data_read(opaque, addr, 4);
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}
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/* i440FX PCI bridge */
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void i440fx_init(void)
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{
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PCIBridge *s = &pci_bridge;
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PCIDevice *d;
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register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s);
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register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s);
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register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s);
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register_ioport_write(0xcfc, 4, 2, pci_data_writew, s);
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register_ioport_write(0xcfc, 4, 4, pci_data_writel, s);
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register_ioport_read(0xcfc, 4, 1, pci_data_readb, s);
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register_ioport_read(0xcfc, 4, 2, pci_data_readw, s);
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register_ioport_read(0xcfc, 4, 4, pci_data_readl, s);
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d = pci_register_device("i440FX", sizeof(PCIDevice), 0, 0,
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NULL, NULL);
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d->config[0x00] = 0x86; // vendor_id
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d->config[0x01] = 0x80;
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d->config[0x02] = 0x37; // device_id
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d->config[0x03] = 0x12;
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d->config[0x08] = 0x02; // revision
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d->config[0x0a] = 0x04; // class_sub = pci2pci
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d->config[0x0b] = 0x06; // class_base = PCI_bridge
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d->config[0x0c] = 0x01; // line_size in 32 bit words
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d->config[0x0e] = 0x01; // header_type
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}
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/* PIIX3 PCI to ISA bridge */
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typedef struct PIIX3State {
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PCIDevice dev;
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} PIIX3State;
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PIIX3State *piix3_state;
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static void piix3_reset(PIIX3State *d)
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{
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uint8_t *pci_conf = d->dev.config;
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pci_conf[0x04] = 0x07; // master, memory and I/O
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pci_conf[0x05] = 0x00;
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pci_conf[0x06] = 0x00;
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pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
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pci_conf[0x4c] = 0x4d;
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pci_conf[0x4e] = 0x03;
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pci_conf[0x4f] = 0x00;
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pci_conf[0x60] = 0x80;
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pci_conf[0x69] = 0x02;
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pci_conf[0x70] = 0x80;
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pci_conf[0x76] = 0x0c;
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pci_conf[0x77] = 0x0c;
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pci_conf[0x78] = 0x02;
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pci_conf[0x79] = 0x00;
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pci_conf[0x80] = 0x00;
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pci_conf[0x82] = 0x00;
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pci_conf[0xa0] = 0x08;
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pci_conf[0xa0] = 0x08;
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pci_conf[0xa2] = 0x00;
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pci_conf[0xa3] = 0x00;
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pci_conf[0xa4] = 0x00;
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pci_conf[0xa5] = 0x00;
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pci_conf[0xa6] = 0x00;
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pci_conf[0xa7] = 0x00;
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pci_conf[0xa8] = 0x0f;
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pci_conf[0xaa] = 0x00;
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pci_conf[0xab] = 0x00;
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pci_conf[0xac] = 0x00;
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pci_conf[0xae] = 0x00;
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}
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|
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void piix3_init(void)
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{
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PIIX3State *d;
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uint8_t *pci_conf;
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d = (PIIX3State *)pci_register_device("PIIX3", sizeof(PIIX3State),
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0, -1,
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NULL, NULL);
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piix3_state = d;
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pci_conf = d->dev.config;
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pci_conf[0x00] = 0x86; // Intel
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pci_conf[0x01] = 0x80;
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pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
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pci_conf[0x03] = 0x70;
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pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
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pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
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pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
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piix3_reset(d);
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}
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|
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/* PREP pci init */
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|
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static inline void set_config(PCIBridge *s, target_phys_addr_t addr)
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{
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int devfn, i;
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for(i = 0; i < 11; i++) {
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if ((addr & (1 << (11 + i))) != 0)
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break;
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}
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devfn = ((addr >> 8) & 7) | (i << 3);
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s->config_reg = 0x80000000 | (addr & 0xfc) | (devfn << 8);
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}
|
|
|
|
static void PPC_PCIIO_writeb (target_phys_addr_t addr, uint32_t val)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
set_config(s, addr);
|
|
pci_data_write(s, addr, val, 1);
|
|
}
|
|
|
|
static void PPC_PCIIO_writew (target_phys_addr_t addr, uint32_t val)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
set_config(s, addr);
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
val = bswap16(val);
|
|
#endif
|
|
pci_data_write(s, addr, val, 2);
|
|
}
|
|
|
|
static void PPC_PCIIO_writel (target_phys_addr_t addr, uint32_t val)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
set_config(s, addr);
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
val = bswap32(val);
|
|
#endif
|
|
pci_data_write(s, addr, val, 4);
|
|
}
|
|
|
|
static uint32_t PPC_PCIIO_readb (target_phys_addr_t addr)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
uint32_t val;
|
|
set_config(s, addr);
|
|
val = pci_data_read(s, addr, 1);
|
|
return val;
|
|
}
|
|
|
|
static uint32_t PPC_PCIIO_readw (target_phys_addr_t addr)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
uint32_t val;
|
|
set_config(s, addr);
|
|
val = pci_data_read(s, addr, 2);
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
val = bswap16(val);
|
|
#endif
|
|
return val;
|
|
}
|
|
|
|
static uint32_t PPC_PCIIO_readl (target_phys_addr_t addr)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
uint32_t val;
|
|
set_config(s, addr);
|
|
val = pci_data_read(s, addr, 4);
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
val = bswap32(val);
|
|
#endif
|
|
return val;
|
|
}
|
|
|
|
static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
|
|
&PPC_PCIIO_writeb,
|
|
&PPC_PCIIO_writew,
|
|
&PPC_PCIIO_writel,
|
|
};
|
|
|
|
static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
|
|
&PPC_PCIIO_readb,
|
|
&PPC_PCIIO_readw,
|
|
&PPC_PCIIO_readl,
|
|
};
|
|
|
|
void pci_prep_init(void)
|
|
{
|
|
PCIDevice *d;
|
|
int PPC_io_memory;
|
|
|
|
PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read, PPC_PCIIO_write);
|
|
cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
|
|
|
|
d = pci_register_device("PREP PCI Bridge", sizeof(PCIDevice), 0, 0,
|
|
NULL, NULL);
|
|
|
|
/* XXX: put correct IDs */
|
|
d->config[0x00] = 0x11; // vendor_id
|
|
d->config[0x01] = 0x10;
|
|
d->config[0x02] = 0x26; // device_id
|
|
d->config[0x03] = 0x00;
|
|
d->config[0x08] = 0x02; // revision
|
|
d->config[0x0a] = 0x04; // class_sub = pci2pci
|
|
d->config[0x0b] = 0x06; // class_base = PCI_bridge
|
|
d->config[0x0e] = 0x01; // header_type
|
|
}
|
|
|
|
|
|
/* pmac pci init */
|
|
|
|
static void pci_pmac_config_writel (target_phys_addr_t addr, uint32_t val)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
val = bswap32(val);
|
|
#endif
|
|
s->config_reg = val;
|
|
}
|
|
|
|
static uint32_t pci_pmac_config_readl (target_phys_addr_t addr)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
uint32_t val;
|
|
|
|
val = s->config_reg;
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
val = bswap32(val);
|
|
#endif
|
|
return val;
|
|
}
|
|
|
|
static CPUWriteMemoryFunc *pci_pmac_config_write[] = {
|
|
&pci_pmac_config_writel,
|
|
&pci_pmac_config_writel,
|
|
&pci_pmac_config_writel,
|
|
};
|
|
|
|
static CPUReadMemoryFunc *pci_pmac_config_read[] = {
|
|
&pci_pmac_config_readl,
|
|
&pci_pmac_config_readl,
|
|
&pci_pmac_config_readl,
|
|
};
|
|
|
|
static void pci_pmac_writeb (target_phys_addr_t addr, uint32_t val)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
pci_data_write(s, addr, val, 1);
|
|
}
|
|
|
|
static void pci_pmac_writew (target_phys_addr_t addr, uint32_t val)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
val = bswap16(val);
|
|
#endif
|
|
pci_data_write(s, addr, val, 2);
|
|
}
|
|
|
|
static void pci_pmac_writel (target_phys_addr_t addr, uint32_t val)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
val = bswap32(val);
|
|
#endif
|
|
pci_data_write(s, addr, val, 4);
|
|
}
|
|
|
|
static uint32_t pci_pmac_readb (target_phys_addr_t addr)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
uint32_t val;
|
|
val = pci_data_read(s, addr, 1);
|
|
return val;
|
|
}
|
|
|
|
static uint32_t pci_pmac_readw (target_phys_addr_t addr)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
uint32_t val;
|
|
val = pci_data_read(s, addr, 2);
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
val = bswap16(val);
|
|
#endif
|
|
return val;
|
|
}
|
|
|
|
static uint32_t pci_pmac_readl (target_phys_addr_t addr)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
uint32_t val;
|
|
|
|
val = pci_data_read(s, addr, 4);
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
val = bswap32(val);
|
|
#endif
|
|
return val;
|
|
}
|
|
|
|
static CPUWriteMemoryFunc *pci_pmac_write[] = {
|
|
&pci_pmac_writeb,
|
|
&pci_pmac_writew,
|
|
&pci_pmac_writel,
|
|
};
|
|
|
|
static CPUReadMemoryFunc *pci_pmac_read[] = {
|
|
&pci_pmac_readb,
|
|
&pci_pmac_readw,
|
|
&pci_pmac_readl,
|
|
};
|
|
|
|
void pci_pmac_init(void)
|
|
{
|
|
PCIDevice *d;
|
|
int pci_mem_config, pci_mem_data;
|
|
|
|
pci_mem_config = cpu_register_io_memory(0, pci_pmac_config_read,
|
|
pci_pmac_config_write);
|
|
pci_mem_data = cpu_register_io_memory(0, pci_pmac_read, pci_pmac_write);
|
|
|
|
cpu_register_physical_memory(0xfec00000, 0x1000, pci_mem_config);
|
|
cpu_register_physical_memory(0xfee00000, 0x1000, pci_mem_data);
|
|
|
|
d = pci_register_device("MPC106", sizeof(PCIDevice), 0, 0,
|
|
NULL, NULL);
|
|
|
|
/* same values as PearPC - check this */
|
|
d->config[0x00] = 0x11; // vendor_id
|
|
d->config[0x01] = 0x10;
|
|
d->config[0x02] = 0x26; // device_id
|
|
d->config[0x03] = 0x00;
|
|
d->config[0x08] = 0x02; // revision
|
|
d->config[0x0a] = 0x04; // class_sub = pci2pci
|
|
d->config[0x0b] = 0x06; // class_base = PCI_bridge
|
|
d->config[0x0e] = 0x01; // header_type
|
|
|
|
d->config[0x18] = 0x0; // primary_bus
|
|
d->config[0x19] = 0x1; // secondary_bus
|
|
d->config[0x1a] = 0x1; // subordinate_bus
|
|
d->config[0x1c] = 0x10; // io_base
|
|
d->config[0x1d] = 0x20; // io_limit
|
|
|
|
d->config[0x20] = 0x80; // memory_base
|
|
d->config[0x21] = 0x80;
|
|
d->config[0x22] = 0x90; // memory_limit
|
|
d->config[0x23] = 0x80;
|
|
|
|
d->config[0x24] = 0x00; // prefetchable_memory_base
|
|
d->config[0x25] = 0x84;
|
|
d->config[0x26] = 0x00; // prefetchable_memory_limit
|
|
d->config[0x27] = 0x85;
|
|
}
|
|
|
|
/***********************************************************/
|
|
/* generic PCI irq support */
|
|
|
|
/* return the global irq number corresponding to a given device irq
|
|
pin. We could also use the bus number to have a more precise
|
|
mapping. */
|
|
static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
|
|
{
|
|
int slot_addend;
|
|
slot_addend = (pci_dev->devfn >> 3);
|
|
return (irq_num + slot_addend) & 3;
|
|
}
|
|
|
|
/* 0 <= irq_num <= 3. level must be 0 or 1 */
|
|
#ifdef TARGET_PPC
|
|
void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
|
|
{
|
|
}
|
|
#else
|
|
void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
|
|
{
|
|
int irq_index, shift, pic_irq, pic_level;
|
|
uint32_t *p;
|
|
|
|
irq_num = pci_slot_get_pirq(pci_dev, irq_num);
|
|
irq_index = pci_dev->irq_index;
|
|
p = &pci_irq_levels[irq_num][irq_index >> 5];
|
|
shift = (irq_index & 0x1f);
|
|
*p = (*p & ~(1 << shift)) | (level << shift);
|
|
|
|
/* now we change the pic irq level according to the piix irq mappings */
|
|
pic_irq = piix3_state->dev.config[0x60 + irq_num];
|
|
if (pic_irq < 16) {
|
|
/* the pic level is the logical OR of all the PCI irqs mapped
|
|
to it */
|
|
pic_level = 0;
|
|
#if (PCI_IRQ_WORDS == 2)
|
|
pic_level = ((pci_irq_levels[irq_num][0] |
|
|
pci_irq_levels[irq_num][1]) != 0);
|
|
#else
|
|
{
|
|
int i;
|
|
pic_level = 0;
|
|
for(i = 0; i < PCI_IRQ_WORDS; i++) {
|
|
if (pci_irq_levels[irq_num][i]) {
|
|
pic_level = 1;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
pic_set_irq(pic_irq, pic_level);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/***********************************************************/
|
|
/* monitor info on PCI */
|
|
|
|
static void pci_info_device(PCIDevice *d)
|
|
{
|
|
int i, class;
|
|
PCIIORegion *r;
|
|
|
|
printf(" Bus %2d, device %3d, function %d:\n",
|
|
d->bus_num, d->devfn >> 3, d->devfn & 7);
|
|
class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
|
|
printf(" ");
|
|
switch(class) {
|
|
case 0x0101:
|
|
printf("IDE controller");
|
|
break;
|
|
case 0x0200:
|
|
printf("Ethernet controller");
|
|
break;
|
|
case 0x0300:
|
|
printf("VGA controller");
|
|
break;
|
|
default:
|
|
printf("Class %04x", class);
|
|
break;
|
|
}
|
|
printf(": PCI device %04x:%04x\n",
|
|
le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
|
|
le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
|
|
|
|
if (d->config[PCI_INTERRUPT_PIN] != 0) {
|
|
printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
|
|
}
|
|
for(i = 0;i < 6; i++) {
|
|
r = &d->io_regions[i];
|
|
if (r->size != 0) {
|
|
printf(" BAR%d: ", i);
|
|
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
|
printf("I/O at 0x%04x [0x%04x].\n",
|
|
r->addr, r->addr + r->size - 1);
|
|
} else {
|
|
printf("32 bit memory at 0x%08x [0x%08x].\n",
|
|
r->addr, r->addr + r->size - 1);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void pci_info(void)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
PCIDevice **bus;
|
|
int bus_num, devfn;
|
|
|
|
for(bus_num = 0; bus_num < 256; bus_num++) {
|
|
bus = s->pci_bus[bus_num];
|
|
if (bus) {
|
|
for(devfn = 0; devfn < 256; devfn++) {
|
|
if (bus[devfn])
|
|
pci_info_device(bus[devfn]);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/***********************************************************/
|
|
/* XXX: the following should be moved to the PC BIOS */
|
|
|
|
static uint32_t isa_inb(uint32_t addr)
|
|
{
|
|
return cpu_inb(cpu_single_env, addr);
|
|
}
|
|
|
|
static void isa_outb(uint32_t val, uint32_t addr)
|
|
{
|
|
cpu_outb(cpu_single_env, addr, val);
|
|
}
|
|
|
|
static uint32_t isa_inw(uint32_t addr)
|
|
{
|
|
return cpu_inw(cpu_single_env, addr);
|
|
}
|
|
|
|
static void isa_outw(uint32_t val, uint32_t addr)
|
|
{
|
|
cpu_outw(cpu_single_env, addr, val);
|
|
}
|
|
|
|
static uint32_t isa_inl(uint32_t addr)
|
|
{
|
|
return cpu_inl(cpu_single_env, addr);
|
|
}
|
|
|
|
static void isa_outl(uint32_t val, uint32_t addr)
|
|
{
|
|
cpu_outl(cpu_single_env, addr, val);
|
|
}
|
|
|
|
static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
s->config_reg = 0x80000000 | (d->bus_num << 16) |
|
|
(d->devfn << 8) | addr;
|
|
pci_data_write(s, 0, val, 4);
|
|
}
|
|
|
|
static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
s->config_reg = 0x80000000 | (d->bus_num << 16) |
|
|
(d->devfn << 8) | (addr & ~3);
|
|
pci_data_write(s, addr & 3, val, 2);
|
|
}
|
|
|
|
static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
s->config_reg = 0x80000000 | (d->bus_num << 16) |
|
|
(d->devfn << 8) | (addr & ~3);
|
|
pci_data_write(s, addr & 3, val, 1);
|
|
}
|
|
|
|
static uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
s->config_reg = 0x80000000 | (d->bus_num << 16) |
|
|
(d->devfn << 8) | addr;
|
|
return pci_data_read(s, 0, 4);
|
|
}
|
|
|
|
static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
s->config_reg = 0x80000000 | (d->bus_num << 16) |
|
|
(d->devfn << 8) | (addr & ~3);
|
|
return pci_data_read(s, addr & 3, 2);
|
|
}
|
|
|
|
static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
s->config_reg = 0x80000000 | (d->bus_num << 16) |
|
|
(d->devfn << 8) | (addr & ~3);
|
|
return pci_data_read(s, addr & 3, 1);
|
|
}
|
|
|
|
static uint32_t pci_bios_io_addr;
|
|
static uint32_t pci_bios_mem_addr;
|
|
/* host irqs corresponding to PCI irqs A-D */
|
|
static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
|
|
|
|
static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
|
|
{
|
|
PCIIORegion *r;
|
|
uint16_t cmd;
|
|
|
|
pci_config_writel(d, 0x10 + region_num * 4, addr);
|
|
r = &d->io_regions[region_num];
|
|
|
|
/* enable memory mappings */
|
|
cmd = pci_config_readw(d, PCI_COMMAND);
|
|
if (r->type & PCI_ADDRESS_SPACE_IO)
|
|
cmd |= 1;
|
|
else
|
|
cmd |= 2;
|
|
pci_config_writew(d, PCI_COMMAND, cmd);
|
|
}
|
|
|
|
static void pci_bios_init_device(PCIDevice *d)
|
|
{
|
|
int class;
|
|
PCIIORegion *r;
|
|
uint32_t *paddr;
|
|
int i, pin, pic_irq, vendor_id, device_id;
|
|
|
|
class = pci_config_readw(d, PCI_CLASS_DEVICE);
|
|
switch(class) {
|
|
case 0x0101:
|
|
vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
|
|
device_id = pci_config_readw(d, PCI_DEVICE_ID);
|
|
if (vendor_id == 0x8086 && device_id == 0x7010) {
|
|
/* PIIX3 IDE */
|
|
pci_config_writew(d, PCI_COMMAND, PCI_COMMAND_IO);
|
|
pci_config_writew(d, 0x40, 0x8000); // enable IDE0
|
|
} else {
|
|
/* IDE: we map it as in ISA mode */
|
|
pci_set_io_region_addr(d, 0, 0x1f0);
|
|
pci_set_io_region_addr(d, 1, 0x3f4);
|
|
pci_set_io_region_addr(d, 2, 0x170);
|
|
pci_set_io_region_addr(d, 3, 0x374);
|
|
}
|
|
break;
|
|
case 0x0300:
|
|
/* VGA: map frame buffer to default Bochs VBE address */
|
|
pci_set_io_region_addr(d, 0, 0xE0000000);
|
|
break;
|
|
default:
|
|
/* default memory mappings */
|
|
for(i = 0; i < 6; i++) {
|
|
r = &d->io_regions[i];
|
|
if (r->size) {
|
|
if (r->type & PCI_ADDRESS_SPACE_IO)
|
|
paddr = &pci_bios_io_addr;
|
|
else
|
|
paddr = &pci_bios_mem_addr;
|
|
*paddr = (*paddr + r->size - 1) & ~(r->size - 1);
|
|
pci_set_io_region_addr(d, i, *paddr);
|
|
*paddr += r->size;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
|
|
/* map the interrupt */
|
|
pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
|
|
if (pin != 0) {
|
|
pin = pci_slot_get_pirq(d, pin - 1);
|
|
pic_irq = pci_irqs[pin];
|
|
pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* This function initializes the PCI devices as a normal PCI BIOS
|
|
* would do. It is provided just in case the BIOS has no support for
|
|
* PCI.
|
|
*/
|
|
void pci_bios_init(void)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
PCIDevice **bus;
|
|
int bus_num, devfn, i, irq;
|
|
uint8_t elcr[2];
|
|
|
|
pci_bios_io_addr = 0xc000;
|
|
pci_bios_mem_addr = 0xf0000000;
|
|
|
|
/* activate IRQ mappings */
|
|
elcr[0] = 0x00;
|
|
elcr[1] = 0x00;
|
|
for(i = 0; i < 4; i++) {
|
|
irq = pci_irqs[i];
|
|
/* set to trigger level */
|
|
elcr[irq >> 3] |= (1 << (irq & 7));
|
|
/* activate irq remapping in PIIX */
|
|
pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
|
|
}
|
|
isa_outb(elcr[0], 0x4d0);
|
|
isa_outb(elcr[1], 0x4d1);
|
|
|
|
for(bus_num = 0; bus_num < 256; bus_num++) {
|
|
bus = s->pci_bus[bus_num];
|
|
if (bus) {
|
|
for(devfn = 0; devfn < 256; devfn++) {
|
|
if (bus[devfn])
|
|
pci_bios_init_device(bus[devfn]);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* This function initializes the PCI devices as a normal PCI BIOS
|
|
* would do. It is provided just in case the BIOS has no support for
|
|
* PCI.
|
|
*/
|
|
void pci_ppc_bios_init(void)
|
|
{
|
|
PCIBridge *s = &pci_bridge;
|
|
PCIDevice **bus;
|
|
int bus_num, devfn, i, irq;
|
|
uint8_t elcr[2];
|
|
|
|
pci_bios_io_addr = 0xc000;
|
|
pci_bios_mem_addr = 0xc0000000;
|
|
|
|
#if 0
|
|
/* activate IRQ mappings */
|
|
elcr[0] = 0x00;
|
|
elcr[1] = 0x00;
|
|
for(i = 0; i < 4; i++) {
|
|
irq = pci_irqs[i];
|
|
/* set to trigger level */
|
|
elcr[irq >> 3] |= (1 << (irq & 7));
|
|
/* activate irq remapping in PIIX */
|
|
pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
|
|
}
|
|
isa_outb(elcr[0], 0x4d0);
|
|
isa_outb(elcr[1], 0x4d1);
|
|
#endif
|
|
|
|
for(bus_num = 0; bus_num < 256; bus_num++) {
|
|
bus = s->pci_bus[bus_num];
|
|
if (bus) {
|
|
for(devfn = 0; devfn < 256; devfn++) {
|
|
if (bus[devfn])
|
|
pci_bios_init_device(bus[devfn]);
|
|
}
|
|
}
|
|
}
|
|
}
|