Currently the libqos PCI layer includes accessor helpers for 8, 16 and 32 bit reads and writes. It's likely that we'll want 64-bit accesses in the future (plenty of modern peripherals will have 64-bit reigsters). This adds them. For PIO (not MMIO) accesses on the PC backend, this is implemented as two 32-bit ins or outs. That's not ideal but AFAICT x86 doesn't have 64-bit versions of in and out. This patch also converts the single current user of 64-bit accesses - virtio-pci.c to use the new mechanism, rather than a sequence of 8 byte reads. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org>
182 lines
4.3 KiB
C
182 lines
4.3 KiB
C
/*
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* libqos PCI bindings for PC
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*
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* Copyright IBM, Corp. 2012-2013
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*
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* Authors:
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* Anthony Liguori <aliguori@us.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "libqtest.h"
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#include "libqos/pci-pc.h"
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#include "hw/pci/pci_regs.h"
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#include "qemu-common.h"
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#define ACPI_PCIHP_ADDR 0xae00
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#define PCI_EJ_BASE 0x0008
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typedef struct QPCIBusPC
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{
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QPCIBus bus;
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} QPCIBusPC;
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static uint8_t qpci_pc_pio_readb(QPCIBus *bus, uint32_t addr)
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{
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return inb(addr);
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}
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static void qpci_pc_pio_writeb(QPCIBus *bus, uint32_t addr, uint8_t val)
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{
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outb(addr, val);
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}
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static uint16_t qpci_pc_pio_readw(QPCIBus *bus, uint32_t addr)
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{
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return inw(addr);
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}
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static void qpci_pc_pio_writew(QPCIBus *bus, uint32_t addr, uint16_t val)
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{
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outw(addr, val);
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}
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static uint32_t qpci_pc_pio_readl(QPCIBus *bus, uint32_t addr)
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{
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return inl(addr);
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}
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static void qpci_pc_pio_writel(QPCIBus *bus, uint32_t addr, uint32_t val)
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{
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outl(addr, val);
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}
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static uint64_t qpci_pc_pio_readq(QPCIBus *bus, uint32_t addr)
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{
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return (uint64_t)inl(addr) + ((uint64_t)inl(addr + 4) << 32);
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}
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static void qpci_pc_pio_writeq(QPCIBus *bus, uint32_t addr, uint64_t val)
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{
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outl(addr, val & 0xffffffff);
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outl(addr + 4, val >> 32);
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}
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static void qpci_pc_memread(QPCIBus *bus, uint32_t addr, void *buf, size_t len)
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{
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memread(addr, buf, len);
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}
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static void qpci_pc_memwrite(QPCIBus *bus, uint32_t addr,
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const void *buf, size_t len)
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{
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memwrite(addr, buf, len);
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}
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static uint8_t qpci_pc_config_readb(QPCIBus *bus, int devfn, uint8_t offset)
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{
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outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
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return inb(0xcfc);
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}
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static uint16_t qpci_pc_config_readw(QPCIBus *bus, int devfn, uint8_t offset)
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{
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outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
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return inw(0xcfc);
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}
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static uint32_t qpci_pc_config_readl(QPCIBus *bus, int devfn, uint8_t offset)
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{
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outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
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return inl(0xcfc);
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}
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static void qpci_pc_config_writeb(QPCIBus *bus, int devfn, uint8_t offset, uint8_t value)
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{
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outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
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outb(0xcfc, value);
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}
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static void qpci_pc_config_writew(QPCIBus *bus, int devfn, uint8_t offset, uint16_t value)
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{
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outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
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outw(0xcfc, value);
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}
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static void qpci_pc_config_writel(QPCIBus *bus, int devfn, uint8_t offset, uint32_t value)
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{
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outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
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outl(0xcfc, value);
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}
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QPCIBus *qpci_init_pc(QGuestAllocator *alloc)
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{
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QPCIBusPC *ret;
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ret = g_malloc(sizeof(*ret));
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ret->bus.pio_readb = qpci_pc_pio_readb;
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ret->bus.pio_readw = qpci_pc_pio_readw;
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ret->bus.pio_readl = qpci_pc_pio_readl;
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ret->bus.pio_readq = qpci_pc_pio_readq;
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ret->bus.pio_writeb = qpci_pc_pio_writeb;
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ret->bus.pio_writew = qpci_pc_pio_writew;
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ret->bus.pio_writel = qpci_pc_pio_writel;
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ret->bus.pio_writeq = qpci_pc_pio_writeq;
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ret->bus.memread = qpci_pc_memread;
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ret->bus.memwrite = qpci_pc_memwrite;
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ret->bus.config_readb = qpci_pc_config_readb;
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ret->bus.config_readw = qpci_pc_config_readw;
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ret->bus.config_readl = qpci_pc_config_readl;
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ret->bus.config_writeb = qpci_pc_config_writeb;
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ret->bus.config_writew = qpci_pc_config_writew;
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ret->bus.config_writel = qpci_pc_config_writel;
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ret->bus.pio_alloc_ptr = 0xc000;
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ret->bus.mmio_alloc_ptr = 0xE0000000;
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ret->bus.mmio_limit = 0x100000000ULL;
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return &ret->bus;
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}
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void qpci_free_pc(QPCIBus *bus)
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{
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QPCIBusPC *s = container_of(bus, QPCIBusPC, bus);
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g_free(s);
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}
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void qpci_unplug_acpi_device_test(const char *id, uint8_t slot)
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{
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QDict *response;
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char *cmd;
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cmd = g_strdup_printf("{'execute': 'device_del',"
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" 'arguments': {"
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" 'id': '%s'"
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"}}", id);
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response = qmp(cmd);
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g_free(cmd);
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g_assert(response);
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g_assert(!qdict_haskey(response, "error"));
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QDECREF(response);
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outb(ACPI_PCIHP_ADDR + PCI_EJ_BASE, 1 << slot);
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response = qmp("");
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g_assert(response);
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g_assert(qdict_haskey(response, "event"));
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g_assert(!strcmp(qdict_get_str(response, "event"), "DEVICE_DELETED"));
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QDECREF(response);
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}
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