1f26c75191
An Event-Based Branch (EBB) allows applications to change the NIA when a event-based exception occurs. Event-based exceptions are enabled by setting the Branch Event Status and Control Register (BESCR). If the event-based exception is enabled when the exception occurs, an EBB happens. The following operations happens during an EBB: - Global Enable (GE) bit of BESCR is set to 0; - bits 0-61 of the Event-Based Branch Return Register (EBBRR) are set to the the effective address of the NIA that would have executed if the EBB didn't happen; - Instruction fetch and execution will continue in the effective address contained in the Event-Based Branch Handler Register (EBBHR). The EBB Handler will process the event and then execute the Return From Event-Based Branch (rfebb) instruction. rfebb sets BESCR_GE and then redirects execution to the address pointed in EBBRR. This process is described in the PowerISA v3.1, Book II, Chapter 6 [1]. This patch implements the rfebb instruction. Descriptions of all relevant BESCR bits are also added - this patch is only using BESCR_GE, but the next patches will use the remaining bits. [1] https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20211201151734.654994-9-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
34 lines
731 B
C++
34 lines
731 B
C++
/*
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* Power ISA decode for branch instructions
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*
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* Copyright IBM Corp. 2021
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*
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* Authors:
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* Daniel Henrique Barboza <danielhb413@gmail.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
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static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg)
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{
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REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
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gen_icount_io_start(ctx);
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gen_update_cfar(ctx, ctx->cia);
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gen_helper_rfebb(cpu_env, cpu_gpr[arg->s]);
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ctx->base.is_jmp = DISAS_CHAIN;
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return true;
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}
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#else
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static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg)
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{
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gen_invalid(ctx);
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return true;
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}
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#endif
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