Add masks and opcodes for decoding TriCore instructions. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1409572800-4116-6-git-send-email-kbastian@mail.uni-paderborn.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
267 lines
7.2 KiB
C
267 lines
7.2 KiB
C
/*
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* TriCore emulation for qemu: main translation routines.
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*
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* Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "disas/disas.h"
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#include "tcg-op.h"
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#include "exec/cpu_ldst.h"
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#include "exec/helper-proto.h"
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#include "exec/helper-gen.h"
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#include "tricore-opcodes.h"
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/*
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* TCG registers
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*/
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static TCGv cpu_PC;
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static TCGv cpu_PCXI;
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static TCGv cpu_PSW;
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static TCGv cpu_ICR;
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/* GPR registers */
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static TCGv cpu_gpr_a[16];
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static TCGv cpu_gpr_d[16];
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/* PSW Flag cache */
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static TCGv cpu_PSW_C;
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static TCGv cpu_PSW_V;
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static TCGv cpu_PSW_SV;
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static TCGv cpu_PSW_AV;
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static TCGv cpu_PSW_SAV;
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/* CPU env */
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static TCGv_ptr cpu_env;
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#include "exec/gen-icount.h"
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static const char *regnames_a[] = {
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"a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
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"a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
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"a12" , "a13" , "a14" , "a15",
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};
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static const char *regnames_d[] = {
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"d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
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"d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
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"d12" , "d13" , "d14" , "d15",
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};
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typedef struct DisasContext {
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struct TranslationBlock *tb;
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target_ulong pc, saved_pc, next_pc;
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uint32_t opcode;
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int singlestep_enabled;
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/* Routine used to access memory */
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int mem_idx;
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uint32_t hflags, saved_hflags;
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int bstate;
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} DisasContext;
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enum {
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BS_NONE = 0,
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BS_STOP = 1,
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BS_BRANCH = 2,
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BS_EXCP = 3,
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};
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void tricore_cpu_dump_state(CPUState *cs, FILE *f,
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fprintf_function cpu_fprintf, int flags)
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{
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TriCoreCPU *cpu = TRICORE_CPU(cs);
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CPUTriCoreState *env = &cpu->env;
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int i;
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cpu_fprintf(f, "PC=%08x\n", env->PC);
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for (i = 0; i < 16; ++i) {
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if ((i & 3) == 0) {
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cpu_fprintf(f, "GPR A%02d:", i);
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}
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cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_a[i], env->gpr_a[i]);
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}
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for (i = 0; i < 16; ++i) {
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if ((i & 3) == 0) {
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cpu_fprintf(f, "GPR D%02d:", i);
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}
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cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_d[i], env->gpr_d[i]);
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}
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}
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static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
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{
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}
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static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
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{
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}
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static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
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{
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/* 16-Bit Instruction */
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if ((ctx->opcode & 0x1) == 0) {
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ctx->next_pc = ctx->pc + 2;
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decode_16Bit_opc(env, ctx);
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/* 32-Bit Instruction */
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} else {
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ctx->next_pc = ctx->pc + 4;
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decode_32Bit_opc(env, ctx);
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}
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}
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static inline void
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gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb,
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int search_pc)
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{
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CPUState *cs = CPU(cpu);
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CPUTriCoreState *env = &cpu->env;
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DisasContext ctx;
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target_ulong pc_start;
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int num_insns;
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uint16_t *gen_opc_end;
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if (search_pc) {
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qemu_log("search pc %d\n", search_pc);
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}
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num_insns = 0;
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pc_start = tb->pc;
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gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
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ctx.pc = pc_start;
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ctx.saved_pc = -1;
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ctx.tb = tb;
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ctx.singlestep_enabled = cs->singlestep_enabled;
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ctx.bstate = BS_NONE;
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ctx.mem_idx = cpu_mmu_index(env);
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tcg_clear_temp_count();
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gen_tb_start();
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while (ctx.bstate == BS_NONE) {
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ctx.opcode = cpu_ldl_code(env, ctx.pc);
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decode_opc(env, &ctx, 0);
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num_insns++;
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if (tcg_ctx.gen_opc_ptr >= gen_opc_end) {
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break;
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}
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if (singlestep) {
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break;
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}
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ctx.pc = ctx.next_pc;
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}
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gen_tb_end(tb, num_insns);
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*tcg_ctx.gen_opc_ptr = INDEX_op_end;
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if (search_pc) {
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printf("done_generating search pc\n");
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} else {
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tb->size = ctx.pc - pc_start;
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tb->icount = num_insns;
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}
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if (tcg_check_temp_count()) {
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printf("LEAK at %08x\n", env->PC);
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}
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#ifdef DEBUG_DISAS
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if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
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qemu_log("IN: %s\n", lookup_symbol(pc_start));
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log_target_disas(env, pc_start, ctx.pc - pc_start, 0);
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qemu_log("\n");
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}
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#endif
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}
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void
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gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
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{
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gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, false);
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}
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void
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gen_intermediate_code_pc(CPUTriCoreState *env, struct TranslationBlock *tb)
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{
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gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, true);
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}
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void
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restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb, int pc_pos)
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{
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env->PC = tcg_ctx.gen_opc_pc[pc_pos];
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}
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/*
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*
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* Initialization
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*
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*/
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void cpu_state_reset(CPUTriCoreState *env)
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{
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/* Reset Regs to Default Value */
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env->PSW = 0xb80;
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}
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static void tricore_tcg_init_csfr(void)
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{
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cpu_PCXI = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUTriCoreState, PCXI), "PCXI");
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cpu_PSW = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUTriCoreState, PSW), "PSW");
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cpu_PC = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUTriCoreState, PC), "PC");
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cpu_ICR = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUTriCoreState, ICR), "ICR");
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}
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void tricore_tcg_init(void)
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{
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int i;
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static int inited;
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if (inited) {
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return;
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}
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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/* reg init */
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for (i = 0 ; i < 16 ; i++) {
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cpu_gpr_a[i] = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUTriCoreState, gpr_a[i]),
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regnames_a[i]);
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}
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for (i = 0 ; i < 16 ; i++) {
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cpu_gpr_d[i] = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUTriCoreState, gpr_d[i]),
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regnames_d[i]);
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}
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tricore_tcg_init_csfr();
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/* init PSW flag cache */
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cpu_PSW_C = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUTriCoreState, PSW_USB_C),
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"PSW_C");
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cpu_PSW_V = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUTriCoreState, PSW_USB_V),
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"PSW_V");
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cpu_PSW_SV = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUTriCoreState, PSW_USB_SV),
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"PSW_SV");
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cpu_PSW_AV = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUTriCoreState, PSW_USB_AV),
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"PSW_AV");
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cpu_PSW_SAV = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUTriCoreState, PSW_USB_SAV),
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"PSW_SAV");
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}
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