All remaining conversions to qdev_realize() are for bus-less devices. Coccinelle script: // only correct for bus-less @dev! @@ expression errp; expression dev; @@ - qdev_init_nofail(dev); + qdev_realize(dev, NULL, &error_fatal); @ depends on !(file in "hw/core/qdev.c") && !(file in "hw/core/bus.c")@ expression errp; expression dev; symbol true; @@ - object_property_set_bool(OBJECT(dev), true, "realized", errp); + qdev_realize(DEVICE(dev), NULL, errp); @ depends on !(file in "hw/core/qdev.c") && !(file in "hw/core/bus.c")@ expression errp; expression dev; symbol true; @@ - object_property_set_bool(dev, true, "realized", errp); + qdev_realize(DEVICE(dev), NULL, errp); Note that Coccinelle chokes on ARMSSE typedef vs. macro in hw/arm/armsse.c. Worked around by temporarily renaming the macro for the spatch run. Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200610053247.1583243-57-armbru@redhat.com>
204 lines
6.4 KiB
C
204 lines
6.4 KiB
C
/*
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* Raspberry Pi emulation (c) 2012 Gregory Estrade
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* Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
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*
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* Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
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* Written by Andrew Baumann
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "cpu.h"
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#include "hw/arm/bcm2836.h"
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#include "hw/arm/raspi_platform.h"
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#include "hw/sysbus.h"
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struct BCM283XInfo {
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const char *name;
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const char *cpu_type;
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hwaddr peri_base; /* Peripheral base address seen by the CPU */
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hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
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int clusterid;
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};
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static const BCM283XInfo bcm283x_socs[] = {
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{
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.name = TYPE_BCM2836,
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.cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"),
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.peri_base = 0x3f000000,
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.ctrl_base = 0x40000000,
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.clusterid = 0xf,
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},
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#ifdef TARGET_AARCH64
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{
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.name = TYPE_BCM2837,
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.cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
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.peri_base = 0x3f000000,
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.ctrl_base = 0x40000000,
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.clusterid = 0x0,
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},
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#endif
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};
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static void bcm2836_init(Object *obj)
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{
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BCM283XState *s = BCM283X(obj);
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BCM283XClass *bc = BCM283X_GET_CLASS(obj);
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const BCM283XInfo *info = bc->info;
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int n;
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for (n = 0; n < BCM283X_NCPUS; n++) {
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object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
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info->cpu_type);
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}
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object_initialize_child(obj, "control", &s->control, TYPE_BCM2836_CONTROL);
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object_initialize_child(obj, "peripherals", &s->peripherals,
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TYPE_BCM2835_PERIPHERALS);
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object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals),
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"board-rev");
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object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals),
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"vcram-size");
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}
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static void bcm2836_realize(DeviceState *dev, Error **errp)
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{
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BCM283XState *s = BCM283X(dev);
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BCM283XClass *bc = BCM283X_GET_CLASS(dev);
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const BCM283XInfo *info = bc->info;
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Object *obj;
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Error *err = NULL;
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int n;
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/* common peripherals from bcm2835 */
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obj = object_property_get_link(OBJECT(dev), "ram", &err);
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if (obj == NULL) {
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error_setg(errp, "%s: required ram link not found: %s",
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__func__, error_get_pretty(err));
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return;
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}
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object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj);
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sysbus_realize(SYS_BUS_DEVICE(&s->peripherals), &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals),
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"sd-bus");
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sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0,
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info->peri_base, 1);
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/* bcm2836 interrupt controller (and mailboxes, etc.) */
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sysbus_realize(SYS_BUS_DEVICE(&s->control), &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, info->ctrl_base);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
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qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
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qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
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for (n = 0; n < BCM283X_NCPUS; n++) {
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/* TODO: this should be converted to a property of ARM_CPU */
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s->cpu[n].core.mp_affinity = (info->clusterid << 8) | n;
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/* set periphbase/CBAR value for CPU-local registers */
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object_property_set_int(OBJECT(&s->cpu[n].core),
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info->peri_base,
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"reset-cbar", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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/* start powered off if not enabled */
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object_property_set_bool(OBJECT(&s->cpu[n].core), n >= s->enabled_cpus,
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"start-powered-off", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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qdev_realize(DEVICE(&s->cpu[n].core), NULL, &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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/* Connect irq/fiq outputs from the interrupt controller. */
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qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n,
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qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_IRQ));
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qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n,
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qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_FIQ));
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/* Connect timers from the CPU to the interrupt controller */
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qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_PHYS,
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qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n));
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qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_VIRT,
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qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n));
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qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_HYP,
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qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n));
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qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC,
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qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n));
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}
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}
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static Property bcm2836_props[] = {
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DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
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BCM283X_NCPUS),
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DEFINE_PROP_END_OF_LIST()
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};
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static void bcm283x_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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BCM283XClass *bc = BCM283X_CLASS(oc);
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bc->info = data;
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dc->realize = bcm2836_realize;
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device_class_set_props(dc, bcm2836_props);
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/* Reason: Must be wired up in code (see raspi_init() function) */
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dc->user_creatable = false;
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}
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static const TypeInfo bcm283x_type_info = {
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.name = TYPE_BCM283X,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(BCM283XState),
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.instance_init = bcm2836_init,
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.class_size = sizeof(BCM283XClass),
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.abstract = true,
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};
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static void bcm2836_register_types(void)
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{
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int i;
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type_register_static(&bcm283x_type_info);
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for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
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TypeInfo ti = {
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.name = bcm283x_socs[i].name,
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.parent = TYPE_BCM283X,
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.class_init = bcm283x_class_init,
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.class_data = (void *) &bcm283x_socs[i],
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};
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type_register(&ti);
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}
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}
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type_init(bcm2836_register_types)
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