The only way object_property_add() can fail is when a property with the same name already exists. Since our property names are all hardcoded, failure is a programming error, and the appropriate way to handle it is passing &error_abort. Same for its variants, except for object_property_add_child(), which additionally fails when the child already has a parent. Parentage is also under program control, so this is a programming error, too. We have a bit over 500 callers. Almost half of them pass &error_abort, slightly fewer ignore errors, one test case handles errors, and the remaining few callers pass them to their own callers. The previous few commits demonstrated once again that ignoring programming errors is a bad idea. Of the few ones that pass on errors, several violate the Error API. The Error ** argument must be NULL, &error_abort, &error_fatal, or a pointer to a variable containing NULL. Passing an argument of the latter kind twice without clearing it in between is wrong: if the first call sets an error, it no longer points to NULL for the second call. ich9_pm_add_properties(), sparc32_ledma_realize(), sparc32_dma_realize(), xilinx_axidma_realize(), xilinx_enet_realize() are wrong that way. When the one appropriate choice of argument is &error_abort, letting users pick the argument is a bad idea. Drop parameter @errp and assert the preconditions instead. There's one exception to "duplicate property name is a programming error": the way object_property_add() implements the magic (and undocumented) "automatic arrayification". Don't drop @errp there. Instead, rename object_property_add() to object_property_try_add(), and add the obvious wrapper object_property_add(). Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200505152926.18877-15-armbru@redhat.com> [Two semantic rebase conflicts resolved]
440 lines
11 KiB
C
440 lines
11 KiB
C
/*
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* QEMU educational PCI device
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*
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* Copyright (c) 2012-2015 Jiri Slaby
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "hw/pci/pci.h"
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#include "hw/hw.h"
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#include "hw/pci/msi.h"
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#include "qemu/timer.h"
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#include "qemu/main-loop.h" /* iothread mutex */
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#include "qemu/module.h"
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#include "qapi/visitor.h"
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#define TYPE_PCI_EDU_DEVICE "edu"
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#define EDU(obj) OBJECT_CHECK(EduState, obj, TYPE_PCI_EDU_DEVICE)
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#define FACT_IRQ 0x00000001
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#define DMA_IRQ 0x00000100
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#define DMA_START 0x40000
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#define DMA_SIZE 4096
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typedef struct {
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PCIDevice pdev;
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MemoryRegion mmio;
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QemuThread thread;
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QemuMutex thr_mutex;
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QemuCond thr_cond;
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bool stopping;
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uint32_t addr4;
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uint32_t fact;
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#define EDU_STATUS_COMPUTING 0x01
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#define EDU_STATUS_IRQFACT 0x80
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uint32_t status;
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uint32_t irq_status;
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#define EDU_DMA_RUN 0x1
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#define EDU_DMA_DIR(cmd) (((cmd) & 0x2) >> 1)
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# define EDU_DMA_FROM_PCI 0
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# define EDU_DMA_TO_PCI 1
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#define EDU_DMA_IRQ 0x4
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struct dma_state {
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dma_addr_t src;
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dma_addr_t dst;
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dma_addr_t cnt;
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dma_addr_t cmd;
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} dma;
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QEMUTimer dma_timer;
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char dma_buf[DMA_SIZE];
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uint64_t dma_mask;
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} EduState;
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static bool edu_msi_enabled(EduState *edu)
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{
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return msi_enabled(&edu->pdev);
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}
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static void edu_raise_irq(EduState *edu, uint32_t val)
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{
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edu->irq_status |= val;
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if (edu->irq_status) {
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if (edu_msi_enabled(edu)) {
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msi_notify(&edu->pdev, 0);
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} else {
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pci_set_irq(&edu->pdev, 1);
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}
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}
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}
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static void edu_lower_irq(EduState *edu, uint32_t val)
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{
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edu->irq_status &= ~val;
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if (!edu->irq_status && !edu_msi_enabled(edu)) {
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pci_set_irq(&edu->pdev, 0);
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}
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}
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static bool within(uint64_t addr, uint64_t start, uint64_t end)
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{
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return start <= addr && addr < end;
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}
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static void edu_check_range(uint64_t addr, uint64_t size1, uint64_t start,
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uint64_t size2)
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{
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uint64_t end1 = addr + size1;
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uint64_t end2 = start + size2;
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if (within(addr, start, end2) &&
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end1 > addr && within(end1, start, end2)) {
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return;
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}
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hw_error("EDU: DMA range 0x%016"PRIx64"-0x%016"PRIx64
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" out of bounds (0x%016"PRIx64"-0x%016"PRIx64")!",
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addr, end1 - 1, start, end2 - 1);
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}
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static dma_addr_t edu_clamp_addr(const EduState *edu, dma_addr_t addr)
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{
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dma_addr_t res = addr & edu->dma_mask;
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if (addr != res) {
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printf("EDU: clamping DMA %#.16"PRIx64" to %#.16"PRIx64"!\n", addr, res);
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}
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return res;
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}
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static void edu_dma_timer(void *opaque)
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{
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EduState *edu = opaque;
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bool raise_irq = false;
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if (!(edu->dma.cmd & EDU_DMA_RUN)) {
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return;
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}
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if (EDU_DMA_DIR(edu->dma.cmd) == EDU_DMA_FROM_PCI) {
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uint64_t dst = edu->dma.dst;
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edu_check_range(dst, edu->dma.cnt, DMA_START, DMA_SIZE);
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dst -= DMA_START;
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pci_dma_read(&edu->pdev, edu_clamp_addr(edu, edu->dma.src),
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edu->dma_buf + dst, edu->dma.cnt);
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} else {
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uint64_t src = edu->dma.src;
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edu_check_range(src, edu->dma.cnt, DMA_START, DMA_SIZE);
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src -= DMA_START;
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pci_dma_write(&edu->pdev, edu_clamp_addr(edu, edu->dma.dst),
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edu->dma_buf + src, edu->dma.cnt);
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}
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edu->dma.cmd &= ~EDU_DMA_RUN;
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if (edu->dma.cmd & EDU_DMA_IRQ) {
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raise_irq = true;
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}
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if (raise_irq) {
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edu_raise_irq(edu, DMA_IRQ);
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}
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}
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static void dma_rw(EduState *edu, bool write, dma_addr_t *val, dma_addr_t *dma,
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bool timer)
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{
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if (write && (edu->dma.cmd & EDU_DMA_RUN)) {
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return;
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}
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if (write) {
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*dma = *val;
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} else {
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*val = *dma;
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}
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if (timer) {
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timer_mod(&edu->dma_timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 100);
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}
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}
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static uint64_t edu_mmio_read(void *opaque, hwaddr addr, unsigned size)
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{
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EduState *edu = opaque;
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uint64_t val = ~0ULL;
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if (addr < 0x80 && size != 4) {
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return val;
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}
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if (addr >= 0x80 && size != 4 && size != 8) {
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return val;
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}
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switch (addr) {
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case 0x00:
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val = 0x010000edu;
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break;
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case 0x04:
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val = edu->addr4;
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break;
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case 0x08:
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qemu_mutex_lock(&edu->thr_mutex);
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val = edu->fact;
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qemu_mutex_unlock(&edu->thr_mutex);
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break;
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case 0x20:
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val = atomic_read(&edu->status);
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break;
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case 0x24:
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val = edu->irq_status;
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break;
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case 0x80:
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dma_rw(edu, false, &val, &edu->dma.src, false);
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break;
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case 0x88:
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dma_rw(edu, false, &val, &edu->dma.dst, false);
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break;
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case 0x90:
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dma_rw(edu, false, &val, &edu->dma.cnt, false);
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break;
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case 0x98:
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dma_rw(edu, false, &val, &edu->dma.cmd, false);
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break;
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}
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return val;
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}
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static void edu_mmio_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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EduState *edu = opaque;
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if (addr < 0x80 && size != 4) {
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return;
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}
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if (addr >= 0x80 && size != 4 && size != 8) {
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return;
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}
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switch (addr) {
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case 0x04:
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edu->addr4 = ~val;
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break;
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case 0x08:
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if (atomic_read(&edu->status) & EDU_STATUS_COMPUTING) {
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break;
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}
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/* EDU_STATUS_COMPUTING cannot go 0->1 concurrently, because it is only
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* set in this function and it is under the iothread mutex.
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*/
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qemu_mutex_lock(&edu->thr_mutex);
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edu->fact = val;
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atomic_or(&edu->status, EDU_STATUS_COMPUTING);
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qemu_cond_signal(&edu->thr_cond);
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qemu_mutex_unlock(&edu->thr_mutex);
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break;
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case 0x20:
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if (val & EDU_STATUS_IRQFACT) {
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atomic_or(&edu->status, EDU_STATUS_IRQFACT);
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} else {
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atomic_and(&edu->status, ~EDU_STATUS_IRQFACT);
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}
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break;
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case 0x60:
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edu_raise_irq(edu, val);
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break;
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case 0x64:
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edu_lower_irq(edu, val);
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break;
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case 0x80:
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dma_rw(edu, true, &val, &edu->dma.src, false);
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break;
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case 0x88:
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dma_rw(edu, true, &val, &edu->dma.dst, false);
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break;
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case 0x90:
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dma_rw(edu, true, &val, &edu->dma.cnt, false);
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break;
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case 0x98:
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if (!(val & EDU_DMA_RUN)) {
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break;
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}
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dma_rw(edu, true, &val, &edu->dma.cmd, true);
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break;
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}
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}
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static const MemoryRegionOps edu_mmio_ops = {
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.read = edu_mmio_read,
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.write = edu_mmio_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 8,
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},
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.impl = {
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.min_access_size = 4,
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.max_access_size = 8,
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},
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};
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/*
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* We purposely use a thread, so that users are forced to wait for the status
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* register.
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*/
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static void *edu_fact_thread(void *opaque)
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{
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EduState *edu = opaque;
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while (1) {
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uint32_t val, ret = 1;
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qemu_mutex_lock(&edu->thr_mutex);
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while ((atomic_read(&edu->status) & EDU_STATUS_COMPUTING) == 0 &&
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!edu->stopping) {
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qemu_cond_wait(&edu->thr_cond, &edu->thr_mutex);
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}
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if (edu->stopping) {
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qemu_mutex_unlock(&edu->thr_mutex);
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break;
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}
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val = edu->fact;
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qemu_mutex_unlock(&edu->thr_mutex);
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while (val > 0) {
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ret *= val--;
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}
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/*
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* We should sleep for a random period here, so that students are
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* forced to check the status properly.
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*/
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qemu_mutex_lock(&edu->thr_mutex);
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edu->fact = ret;
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qemu_mutex_unlock(&edu->thr_mutex);
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atomic_and(&edu->status, ~EDU_STATUS_COMPUTING);
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if (atomic_read(&edu->status) & EDU_STATUS_IRQFACT) {
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qemu_mutex_lock_iothread();
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edu_raise_irq(edu, FACT_IRQ);
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qemu_mutex_unlock_iothread();
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}
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}
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return NULL;
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}
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static void pci_edu_realize(PCIDevice *pdev, Error **errp)
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{
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EduState *edu = EDU(pdev);
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uint8_t *pci_conf = pdev->config;
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pci_config_set_interrupt_pin(pci_conf, 1);
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if (msi_init(pdev, 0, 1, true, false, errp)) {
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return;
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}
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timer_init_ms(&edu->dma_timer, QEMU_CLOCK_VIRTUAL, edu_dma_timer, edu);
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qemu_mutex_init(&edu->thr_mutex);
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qemu_cond_init(&edu->thr_cond);
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qemu_thread_create(&edu->thread, "edu", edu_fact_thread,
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edu, QEMU_THREAD_JOINABLE);
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memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu,
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"edu-mmio", 1 * MiB);
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pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &edu->mmio);
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}
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static void pci_edu_uninit(PCIDevice *pdev)
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{
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EduState *edu = EDU(pdev);
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qemu_mutex_lock(&edu->thr_mutex);
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edu->stopping = true;
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qemu_mutex_unlock(&edu->thr_mutex);
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qemu_cond_signal(&edu->thr_cond);
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qemu_thread_join(&edu->thread);
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qemu_cond_destroy(&edu->thr_cond);
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qemu_mutex_destroy(&edu->thr_mutex);
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timer_del(&edu->dma_timer);
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msi_uninit(pdev);
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}
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static void edu_instance_init(Object *obj)
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{
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EduState *edu = EDU(obj);
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edu->dma_mask = (1UL << 28) - 1;
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object_property_add_uint64_ptr(obj, "dma_mask",
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&edu->dma_mask, OBJ_PROP_FLAG_READWRITE);
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}
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static void edu_class_init(ObjectClass *class, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(class);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(class);
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k->realize = pci_edu_realize;
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k->exit = pci_edu_uninit;
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k->vendor_id = PCI_VENDOR_ID_QEMU;
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k->device_id = 0x11e8;
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k->revision = 0x10;
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k->class_id = PCI_CLASS_OTHERS;
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set_bit(DEVICE_CATEGORY_MISC, dc->categories);
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}
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static void pci_edu_register_types(void)
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{
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static InterfaceInfo interfaces[] = {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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};
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static const TypeInfo edu_info = {
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.name = TYPE_PCI_EDU_DEVICE,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(EduState),
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.instance_init = edu_instance_init,
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.class_init = edu_class_init,
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.interfaces = interfaces,
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};
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type_register_static(&edu_info);
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}
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type_init(pci_edu_register_types)
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