git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3869 c046a42c-6fe2-441c-8c8c-71466251a162
168 lines
4.1 KiB
C
168 lines
4.1 KiB
C
/*
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* QEMU Sparc SBI interrupt controller emulation
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*
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* Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "sun4m.h"
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#include "console.h"
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//#define DEBUG_IRQ
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#ifdef DEBUG_IRQ
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#define DPRINTF(fmt, args...) \
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do { printf("IRQ: " fmt , ##args); } while (0)
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#else
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#define DPRINTF(fmt, args...)
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#endif
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#define MAX_CPUS 16
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#define SBI_NREGS 16
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typedef struct SBIState {
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uint32_t regs[SBI_NREGS];
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uint32_t intreg_pending[MAX_CPUS];
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qemu_irq *cpu_irqs[MAX_CPUS];
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uint32_t pil_out[MAX_CPUS];
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} SBIState;
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#define SBI_SIZE (SBI_NREGS * 4)
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#define SBI_MASK (SBI_SIZE - 1)
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static void sbi_check_interrupts(void *opaque)
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{
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}
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static void sbi_set_irq(void *opaque, int irq, int level)
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{
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}
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static void sbi_set_timer_irq_cpu(void *opaque, int cpu, int level)
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{
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}
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static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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SBIState *s = opaque;
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uint32_t saddr, ret;
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saddr = (addr & SBI_MASK) >> 2;
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switch (saddr) {
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default:
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ret = s->regs[saddr];
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break;
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}
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DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
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return ret;
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}
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static void sbi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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SBIState *s = opaque;
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uint32_t saddr;
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saddr = (addr & SBI_MASK) >> 2;
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DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
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switch (saddr) {
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default:
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s->regs[saddr] = val;
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break;
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}
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}
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static CPUReadMemoryFunc *sbi_mem_read[3] = {
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sbi_mem_readl,
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sbi_mem_readl,
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sbi_mem_readl,
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};
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static CPUWriteMemoryFunc *sbi_mem_write[3] = {
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sbi_mem_writel,
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sbi_mem_writel,
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sbi_mem_writel,
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};
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static void sbi_save(QEMUFile *f, void *opaque)
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{
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SBIState *s = opaque;
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unsigned int i;
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for (i = 0; i < MAX_CPUS; i++) {
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qemu_put_be32s(f, &s->intreg_pending[i]);
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}
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}
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static int sbi_load(QEMUFile *f, void *opaque, int version_id)
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{
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SBIState *s = opaque;
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unsigned int i;
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if (version_id != 1)
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return -EINVAL;
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for (i = 0; i < MAX_CPUS; i++) {
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qemu_get_be32s(f, &s->intreg_pending[i]);
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}
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sbi_check_interrupts(s);
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return 0;
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}
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static void sbi_reset(void *opaque)
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{
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SBIState *s = opaque;
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unsigned int i;
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for (i = 0; i < MAX_CPUS; i++) {
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s->intreg_pending[i] = 0;
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}
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sbi_check_interrupts(s);
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}
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void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,
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qemu_irq **parent_irq)
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{
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unsigned int i;
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int sbi_io_memory;
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SBIState *s;
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s = qemu_mallocz(sizeof(SBIState));
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if (!s)
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return NULL;
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for (i = 0; i < MAX_CPUS; i++) {
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s->cpu_irqs[i] = parent_irq[i];
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}
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sbi_io_memory = cpu_register_io_memory(0, sbi_mem_read, sbi_mem_write, s);
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cpu_register_physical_memory(addr, SBI_SIZE, sbi_io_memory);
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register_savevm("sbi", addr, 1, sbi_save, sbi_load, s);
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qemu_register_reset(sbi_reset, s);
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*irq = qemu_allocate_irqs(sbi_set_irq, s, 32);
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*cpu_irq = qemu_allocate_irqs(sbi_set_timer_irq_cpu, s, MAX_CPUS);
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sbi_reset(s);
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return s;
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}
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