Convert VCMLA (scalar) in the 2reg-scalar-ext group to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200430181003.21682-9-peter.maydell@linaro.org
210 lines
5.7 KiB
C
210 lines
5.7 KiB
C
/*
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* ARM translation: AArch32 Neon instructions
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2005-2007 CodeSourcery
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* Copyright (c) 2007 OpenedHand, Ltd.
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* Copyright (c) 2020 Linaro, Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* This file is intended to be included from translate.c; it uses
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* some macros and definitions provided by that file.
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* It might be possible to convert it to a standalone .c file eventually.
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*/
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/* Include the generated Neon decoder */
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#include "decode-neon-dp.inc.c"
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#include "decode-neon-ls.inc.c"
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#include "decode-neon-shared.inc.c"
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static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
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{
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int opr_sz;
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TCGv_ptr fpst;
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gen_helper_gvec_3_ptr *fn_gvec_ptr;
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if (!dc_isar_feature(aa32_vcma, s)
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|| (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) {
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_simd_r32, s) &&
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((a->vd | a->vn | a->vm) & 0x10)) {
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return false;
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}
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if ((a->vn | a->vm | a->vd) & a->q) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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opr_sz = (1 + a->q) * 8;
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fpst = get_fpstatus_ptr(1);
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fn_gvec_ptr = a->size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah;
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tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
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vfp_reg_offset(1, a->vn),
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vfp_reg_offset(1, a->vm),
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fpst, opr_sz, opr_sz, a->rot,
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fn_gvec_ptr);
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tcg_temp_free_ptr(fpst);
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return true;
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}
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static bool trans_VCADD(DisasContext *s, arg_VCADD *a)
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{
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int opr_sz;
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TCGv_ptr fpst;
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gen_helper_gvec_3_ptr *fn_gvec_ptr;
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if (!dc_isar_feature(aa32_vcma, s)
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|| (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) {
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_simd_r32, s) &&
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((a->vd | a->vn | a->vm) & 0x10)) {
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return false;
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}
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if ((a->vn | a->vm | a->vd) & a->q) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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opr_sz = (1 + a->q) * 8;
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fpst = get_fpstatus_ptr(1);
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fn_gvec_ptr = a->size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh;
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tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
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vfp_reg_offset(1, a->vn),
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vfp_reg_offset(1, a->vm),
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fpst, opr_sz, opr_sz, a->rot,
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fn_gvec_ptr);
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tcg_temp_free_ptr(fpst);
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return true;
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}
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static bool trans_VDOT(DisasContext *s, arg_VDOT *a)
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{
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int opr_sz;
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gen_helper_gvec_3 *fn_gvec;
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if (!dc_isar_feature(aa32_dp, s)) {
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_simd_r32, s) &&
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((a->vd | a->vn | a->vm) & 0x10)) {
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return false;
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}
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if ((a->vn | a->vm | a->vd) & a->q) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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opr_sz = (1 + a->q) * 8;
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fn_gvec = a->u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b;
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tcg_gen_gvec_3_ool(vfp_reg_offset(1, a->vd),
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vfp_reg_offset(1, a->vn),
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vfp_reg_offset(1, a->vm),
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opr_sz, opr_sz, 0, fn_gvec);
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return true;
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}
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static bool trans_VFML(DisasContext *s, arg_VFML *a)
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{
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int opr_sz;
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if (!dc_isar_feature(aa32_fhm, s)) {
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_simd_r32, s) &&
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(a->vd & 0x10)) {
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return false;
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}
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if (a->vd & a->q) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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opr_sz = (1 + a->q) * 8;
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tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
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vfp_reg_offset(a->q, a->vn),
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vfp_reg_offset(a->q, a->vm),
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cpu_env, opr_sz, opr_sz, a->s, /* is_2 == 0 */
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gen_helper_gvec_fmlal_a32);
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return true;
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}
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static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a)
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{
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gen_helper_gvec_3_ptr *fn_gvec_ptr;
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int opr_sz;
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TCGv_ptr fpst;
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if (!dc_isar_feature(aa32_vcma, s)) {
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return false;
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}
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if (a->size == 0 && !dc_isar_feature(aa32_fp16_arith, s)) {
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_simd_r32, s) &&
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((a->vd | a->vn | a->vm) & 0x10)) {
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return false;
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}
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if ((a->vd | a->vn) & a->q) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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fn_gvec_ptr = (a->size ? gen_helper_gvec_fcmlas_idx
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: gen_helper_gvec_fcmlah_idx);
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opr_sz = (1 + a->q) * 8;
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fpst = get_fpstatus_ptr(1);
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tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
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vfp_reg_offset(1, a->vn),
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vfp_reg_offset(1, a->vm),
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fpst, opr_sz, opr_sz,
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(a->index << 2) | a->rot, fn_gvec_ptr);
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tcg_temp_free_ptr(fpst);
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return true;
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}
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