git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4246 c046a42c-6fe2-441c-8c8c-71466251a162
1312 lines
37 KiB
C
1312 lines
37 KiB
C
/*
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* PXA270-based Clamshell PDA platforms.
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Written by Andrzej Zaborowski <balrog@zabor.org>
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*
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* This code is licensed under the GNU GPL v2.
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*/
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#include "hw.h"
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#include "pxa.h"
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#include "arm-misc.h"
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#include "sysemu.h"
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#include "pcmcia.h"
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#include "i2c.h"
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#include "flash.h"
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#include "qemu-timer.h"
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#include "devices.h"
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#include "console.h"
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#include "block.h"
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#include "audio/audio.h"
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#include "boards.h"
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#define spitz_printf(format, ...) \
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fprintf(stderr, "%s: " format, __FUNCTION__, ##__VA_ARGS__)
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#undef REG_FMT
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#if TARGET_PHYS_ADDR_BITS == 32
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#define REG_FMT "0x%02x"
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#else
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#define REG_FMT "0x%02lx"
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#endif
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/* Spitz Flash */
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#define FLASH_BASE 0x0c000000
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#define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */
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#define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */
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#define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */
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#define FLASH_ECCCNTR 0x0c /* ECC byte counter */
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#define FLASH_ECCCLRR 0x10 /* Clear ECC */
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#define FLASH_FLASHIO 0x14 /* Flash I/O */
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#define FLASH_FLASHCTL 0x18 /* Flash Control */
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#define FLASHCTL_CE0 (1 << 0)
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#define FLASHCTL_CLE (1 << 1)
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#define FLASHCTL_ALE (1 << 2)
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#define FLASHCTL_WP (1 << 3)
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#define FLASHCTL_CE1 (1 << 4)
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#define FLASHCTL_RYBY (1 << 5)
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#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
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struct sl_nand_s {
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target_phys_addr_t target_base;
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struct nand_flash_s *nand;
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uint8_t ctl;
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struct ecc_state_s ecc;
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};
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static uint32_t sl_readb(void *opaque, target_phys_addr_t addr)
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{
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struct sl_nand_s *s = (struct sl_nand_s *) opaque;
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int ryby;
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addr -= s->target_base;
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switch (addr) {
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#define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
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case FLASH_ECCLPLB:
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return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
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BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
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#define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to))
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case FLASH_ECCLPUB:
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return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
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BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
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case FLASH_ECCCP:
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return s->ecc.cp;
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case FLASH_ECCCNTR:
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return s->ecc.count & 0xff;
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case FLASH_FLASHCTL:
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nand_getpins(s->nand, &ryby);
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if (ryby)
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return s->ctl | FLASHCTL_RYBY;
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else
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return s->ctl;
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case FLASH_FLASHIO:
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return ecc_digest(&s->ecc, nand_getio(s->nand));
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default:
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spitz_printf("Bad register offset " REG_FMT "\n", addr);
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}
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return 0;
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}
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static uint32_t sl_readl(void *opaque, target_phys_addr_t addr)
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{
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struct sl_nand_s *s = (struct sl_nand_s *) opaque;
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addr -= s->target_base;
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if (addr == FLASH_FLASHIO)
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return ecc_digest(&s->ecc, nand_getio(s->nand)) |
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(ecc_digest(&s->ecc, nand_getio(s->nand)) << 16);
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return sl_readb(opaque, addr);
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}
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static void sl_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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struct sl_nand_s *s = (struct sl_nand_s *) opaque;
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addr -= s->target_base;
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switch (addr) {
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case FLASH_ECCCLRR:
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/* Value is ignored. */
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ecc_reset(&s->ecc);
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break;
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case FLASH_FLASHCTL:
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s->ctl = value & 0xff & ~FLASHCTL_RYBY;
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nand_setpins(s->nand,
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s->ctl & FLASHCTL_CLE,
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s->ctl & FLASHCTL_ALE,
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s->ctl & FLASHCTL_NCE,
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s->ctl & FLASHCTL_WP,
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0);
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break;
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case FLASH_FLASHIO:
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nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff));
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break;
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default:
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spitz_printf("Bad register offset " REG_FMT "\n", addr);
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}
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}
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static void sl_save(QEMUFile *f, void *opaque)
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{
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struct sl_nand_s *s = (struct sl_nand_s *) opaque;
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qemu_put_8s(f, &s->ctl);
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ecc_put(f, &s->ecc);
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}
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static int sl_load(QEMUFile *f, void *opaque, int version_id)
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{
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struct sl_nand_s *s = (struct sl_nand_s *) opaque;
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qemu_get_8s(f, &s->ctl);
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ecc_get(f, &s->ecc);
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return 0;
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}
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enum {
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FLASH_128M,
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FLASH_1024M,
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};
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static void sl_flash_register(struct pxa2xx_state_s *cpu, int size)
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{
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int iomemtype;
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struct sl_nand_s *s;
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CPUReadMemoryFunc *sl_readfn[] = {
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sl_readb,
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sl_readb,
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sl_readl,
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};
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CPUWriteMemoryFunc *sl_writefn[] = {
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sl_writeb,
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sl_writeb,
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sl_writeb,
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};
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s = (struct sl_nand_s *) qemu_mallocz(sizeof(struct sl_nand_s));
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s->target_base = FLASH_BASE;
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s->ctl = 0;
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if (size == FLASH_128M)
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s->nand = nand_init(NAND_MFR_SAMSUNG, 0x73);
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else if (size == FLASH_1024M)
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s->nand = nand_init(NAND_MFR_SAMSUNG, 0xf1);
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iomemtype = cpu_register_io_memory(0, sl_readfn,
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sl_writefn, s);
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cpu_register_physical_memory(s->target_base, 0x40, iomemtype);
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register_savevm("sl_flash", 0, 0, sl_save, sl_load, s);
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}
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/* Spitz Keyboard */
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#define SPITZ_KEY_STROBE_NUM 11
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#define SPITZ_KEY_SENSE_NUM 7
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static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
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12, 17, 91, 34, 36, 38, 39
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};
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static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = {
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88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114
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};
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/* Eighth additional row maps the special keys */
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static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
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{ 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 },
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{ -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 },
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{ 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25, -1 , -1 , -1 },
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{ 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26, -1 , 0x36, -1 },
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{ 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34, -1 , 0x1c, 0x2a, -1 },
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{ 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33, -1 , 0x48, -1 , -1 , 0x38 },
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{ 0x37, 0x3d, -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d, -1 , -1 },
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{ 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 },
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};
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#define SPITZ_GPIO_AK_INT 13 /* Remote control */
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#define SPITZ_GPIO_SYNC 16 /* Sync button */
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#define SPITZ_GPIO_ON_KEY 95 /* Power button */
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#define SPITZ_GPIO_SWA 97 /* Lid */
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#define SPITZ_GPIO_SWB 96 /* Tablet mode */
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/* The special buttons are mapped to unused keys */
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static const int spitz_gpiomap[5] = {
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SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY,
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SPITZ_GPIO_SWA, SPITZ_GPIO_SWB,
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};
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static int spitz_gpio_invert[5] = { 0, 0, 0, 0, 0, };
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struct spitz_keyboard_s {
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qemu_irq sense[SPITZ_KEY_SENSE_NUM];
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qemu_irq *strobe;
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qemu_irq gpiomap[5];
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int keymap[0x80];
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uint16_t keyrow[SPITZ_KEY_SENSE_NUM];
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uint16_t strobe_state;
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uint16_t sense_state;
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uint16_t pre_map[0x100];
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uint16_t modifiers;
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uint16_t imodifiers;
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uint8_t fifo[16];
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int fifopos, fifolen;
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QEMUTimer *kbdtimer;
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};
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static void spitz_keyboard_sense_update(struct spitz_keyboard_s *s)
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{
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int i;
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uint16_t strobe, sense = 0;
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for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) {
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strobe = s->keyrow[i] & s->strobe_state;
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if (strobe) {
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sense |= 1 << i;
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if (!(s->sense_state & (1 << i)))
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qemu_irq_raise(s->sense[i]);
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} else if (s->sense_state & (1 << i))
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qemu_irq_lower(s->sense[i]);
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}
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s->sense_state = sense;
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}
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static void spitz_keyboard_strobe(void *opaque, int line, int level)
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{
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struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
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if (level)
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s->strobe_state |= 1 << line;
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else
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s->strobe_state &= ~(1 << line);
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spitz_keyboard_sense_update(s);
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}
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static void spitz_keyboard_keydown(struct spitz_keyboard_s *s, int keycode)
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{
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int spitz_keycode = s->keymap[keycode & 0x7f];
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if (spitz_keycode == -1)
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return;
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/* Handle the additional keys */
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if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) {
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qemu_set_irq(s->gpiomap[spitz_keycode & 0xf], (keycode < 0x80) ^
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spitz_gpio_invert[spitz_keycode & 0xf]);
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return;
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}
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if (keycode & 0x80)
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s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf));
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else
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s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf);
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spitz_keyboard_sense_update(s);
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}
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#define SHIFT (1 << 7)
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#define CTRL (1 << 8)
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#define FN (1 << 9)
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#define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
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static void spitz_keyboard_handler(struct spitz_keyboard_s *s, int keycode)
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{
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uint16_t code;
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int mapcode;
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switch (keycode) {
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case 0x2a: /* Left Shift */
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s->modifiers |= 1;
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break;
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case 0xaa:
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s->modifiers &= ~1;
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break;
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case 0x36: /* Right Shift */
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s->modifiers |= 2;
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break;
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case 0xb6:
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s->modifiers &= ~2;
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break;
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case 0x1d: /* Control */
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s->modifiers |= 4;
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break;
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case 0x9d:
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s->modifiers &= ~4;
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break;
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case 0x38: /* Alt */
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s->modifiers |= 8;
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break;
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case 0xb8:
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s->modifiers &= ~8;
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break;
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}
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code = s->pre_map[mapcode = ((s->modifiers & 3) ?
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(keycode | SHIFT) :
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(keycode & ~SHIFT))];
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if (code != mapcode) {
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#if 0
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if ((code & SHIFT) && !(s->modifiers & 1))
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QUEUE_KEY(0x2a | (keycode & 0x80));
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if ((code & CTRL ) && !(s->modifiers & 4))
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QUEUE_KEY(0x1d | (keycode & 0x80));
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if ((code & FN ) && !(s->modifiers & 8))
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QUEUE_KEY(0x38 | (keycode & 0x80));
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if ((code & FN ) && (s->modifiers & 1))
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QUEUE_KEY(0x2a | (~keycode & 0x80));
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if ((code & FN ) && (s->modifiers & 2))
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QUEUE_KEY(0x36 | (~keycode & 0x80));
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#else
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if (keycode & 0x80) {
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if ((s->imodifiers & 1 ) && !(s->modifiers & 1))
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QUEUE_KEY(0x2a | 0x80);
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if ((s->imodifiers & 4 ) && !(s->modifiers & 4))
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QUEUE_KEY(0x1d | 0x80);
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if ((s->imodifiers & 8 ) && !(s->modifiers & 8))
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QUEUE_KEY(0x38 | 0x80);
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if ((s->imodifiers & 0x10) && (s->modifiers & 1))
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QUEUE_KEY(0x2a);
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if ((s->imodifiers & 0x20) && (s->modifiers & 2))
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QUEUE_KEY(0x36);
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s->imodifiers = 0;
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} else {
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if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) {
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QUEUE_KEY(0x2a);
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s->imodifiers |= 1;
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}
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if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) {
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QUEUE_KEY(0x1d);
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s->imodifiers |= 4;
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}
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if ((code & FN ) && !((s->modifiers | s->imodifiers) & 8)) {
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QUEUE_KEY(0x38);
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s->imodifiers |= 8;
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}
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if ((code & FN ) && (s->modifiers & 1) &&
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!(s->imodifiers & 0x10)) {
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QUEUE_KEY(0x2a | 0x80);
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s->imodifiers |= 0x10;
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}
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if ((code & FN ) && (s->modifiers & 2) &&
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!(s->imodifiers & 0x20)) {
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QUEUE_KEY(0x36 | 0x80);
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s->imodifiers |= 0x20;
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}
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}
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#endif
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}
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QUEUE_KEY((code & 0x7f) | (keycode & 0x80));
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}
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static void spitz_keyboard_tick(void *opaque)
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{
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struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
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if (s->fifolen) {
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spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]);
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s->fifolen --;
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if (s->fifopos >= 16)
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s->fifopos = 0;
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}
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qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) + ticks_per_sec / 32);
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}
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static void spitz_keyboard_pre_map(struct spitz_keyboard_s *s)
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{
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int i;
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for (i = 0; i < 0x100; i ++)
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s->pre_map[i] = i;
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s->pre_map[0x02 | SHIFT ] = 0x02 | SHIFT; /* exclam */
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s->pre_map[0x28 | SHIFT ] = 0x03 | SHIFT; /* quotedbl */
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s->pre_map[0x04 | SHIFT ] = 0x04 | SHIFT; /* numbersign */
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s->pre_map[0x05 | SHIFT ] = 0x05 | SHIFT; /* dollar */
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s->pre_map[0x06 | SHIFT ] = 0x06 | SHIFT; /* percent */
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s->pre_map[0x08 | SHIFT ] = 0x07 | SHIFT; /* ampersand */
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s->pre_map[0x28 ] = 0x08 | SHIFT; /* apostrophe */
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s->pre_map[0x0a | SHIFT ] = 0x09 | SHIFT; /* parenleft */
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s->pre_map[0x0b | SHIFT ] = 0x0a | SHIFT; /* parenright */
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s->pre_map[0x29 | SHIFT ] = 0x0b | SHIFT; /* asciitilde */
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s->pre_map[0x03 | SHIFT ] = 0x0c | SHIFT; /* at */
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s->pre_map[0xd3 ] = 0x0e | FN; /* Delete */
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s->pre_map[0x3a ] = 0x0f | FN; /* Caps_Lock */
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s->pre_map[0x07 | SHIFT ] = 0x11 | FN; /* asciicircum */
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s->pre_map[0x0d ] = 0x12 | FN; /* equal */
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s->pre_map[0x0d | SHIFT ] = 0x13 | FN; /* plus */
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s->pre_map[0x1a ] = 0x14 | FN; /* bracketleft */
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s->pre_map[0x1b ] = 0x15 | FN; /* bracketright */
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s->pre_map[0x1a | SHIFT ] = 0x16 | FN; /* braceleft */
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s->pre_map[0x1b | SHIFT ] = 0x17 | FN; /* braceright */
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s->pre_map[0x27 ] = 0x22 | FN; /* semicolon */
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s->pre_map[0x27 | SHIFT ] = 0x23 | FN; /* colon */
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s->pre_map[0x09 | SHIFT ] = 0x24 | FN; /* asterisk */
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s->pre_map[0x2b ] = 0x25 | FN; /* backslash */
|
|
s->pre_map[0x2b | SHIFT ] = 0x26 | FN; /* bar */
|
|
s->pre_map[0x0c | SHIFT ] = 0x30 | FN; /* underscore */
|
|
s->pre_map[0x33 | SHIFT ] = 0x33 | FN; /* less */
|
|
s->pre_map[0x35 ] = 0x33 | SHIFT; /* slash */
|
|
s->pre_map[0x34 | SHIFT ] = 0x34 | FN; /* greater */
|
|
s->pre_map[0x35 | SHIFT ] = 0x34 | SHIFT; /* question */
|
|
s->pre_map[0x49 ] = 0x48 | FN; /* Page_Up */
|
|
s->pre_map[0x51 ] = 0x50 | FN; /* Page_Down */
|
|
|
|
s->modifiers = 0;
|
|
s->imodifiers = 0;
|
|
s->fifopos = 0;
|
|
s->fifolen = 0;
|
|
s->kbdtimer = qemu_new_timer(vm_clock, spitz_keyboard_tick, s);
|
|
spitz_keyboard_tick(s);
|
|
}
|
|
|
|
#undef SHIFT
|
|
#undef CTRL
|
|
#undef FN
|
|
|
|
static void spitz_keyboard_save(QEMUFile *f, void *opaque)
|
|
{
|
|
struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
|
|
int i;
|
|
|
|
qemu_put_be16s(f, &s->sense_state);
|
|
qemu_put_be16s(f, &s->strobe_state);
|
|
for (i = 0; i < 5; i ++)
|
|
qemu_put_byte(f, spitz_gpio_invert[i]);
|
|
}
|
|
|
|
static int spitz_keyboard_load(QEMUFile *f, void *opaque, int version_id)
|
|
{
|
|
struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
|
|
int i;
|
|
|
|
qemu_get_be16s(f, &s->sense_state);
|
|
qemu_get_be16s(f, &s->strobe_state);
|
|
for (i = 0; i < 5; i ++)
|
|
spitz_gpio_invert[i] = qemu_get_byte(f);
|
|
|
|
/* Release all pressed keys */
|
|
memset(s->keyrow, 0, sizeof(s->keyrow));
|
|
spitz_keyboard_sense_update(s);
|
|
s->modifiers = 0;
|
|
s->imodifiers = 0;
|
|
s->fifopos = 0;
|
|
s->fifolen = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void spitz_keyboard_register(struct pxa2xx_state_s *cpu)
|
|
{
|
|
int i, j;
|
|
struct spitz_keyboard_s *s;
|
|
|
|
s = (struct spitz_keyboard_s *)
|
|
qemu_mallocz(sizeof(struct spitz_keyboard_s));
|
|
memset(s, 0, sizeof(struct spitz_keyboard_s));
|
|
|
|
for (i = 0; i < 0x80; i ++)
|
|
s->keymap[i] = -1;
|
|
for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++)
|
|
for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++)
|
|
if (spitz_keymap[i][j] != -1)
|
|
s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
|
|
|
|
for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++)
|
|
s->sense[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpio_key_sense[i]];
|
|
|
|
for (i = 0; i < 5; i ++)
|
|
s->gpiomap[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpiomap[i]];
|
|
|
|
s->strobe = qemu_allocate_irqs(spitz_keyboard_strobe, s,
|
|
SPITZ_KEY_STROBE_NUM);
|
|
for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++)
|
|
pxa2xx_gpio_out_set(cpu->gpio, spitz_gpio_key_strobe[i], s->strobe[i]);
|
|
|
|
spitz_keyboard_pre_map(s);
|
|
qemu_add_kbd_event_handler((QEMUPutKBDEvent *) spitz_keyboard_handler, s);
|
|
|
|
register_savevm("spitz_keyboard", 0, 0,
|
|
spitz_keyboard_save, spitz_keyboard_load, s);
|
|
}
|
|
|
|
/* SCOOP devices */
|
|
|
|
struct scoop_info_s {
|
|
target_phys_addr_t target_base;
|
|
qemu_irq handler[16];
|
|
qemu_irq *in;
|
|
uint16_t status;
|
|
uint16_t power;
|
|
uint32_t gpio_level;
|
|
uint32_t gpio_dir;
|
|
uint32_t prev_level;
|
|
|
|
uint16_t mcr;
|
|
uint16_t cdr;
|
|
uint16_t ccr;
|
|
uint16_t irr;
|
|
uint16_t imr;
|
|
uint16_t isr;
|
|
uint16_t gprr;
|
|
};
|
|
|
|
#define SCOOP_MCR 0x00
|
|
#define SCOOP_CDR 0x04
|
|
#define SCOOP_CSR 0x08
|
|
#define SCOOP_CPR 0x0c
|
|
#define SCOOP_CCR 0x10
|
|
#define SCOOP_IRR_IRM 0x14
|
|
#define SCOOP_IMR 0x18
|
|
#define SCOOP_ISR 0x1c
|
|
#define SCOOP_GPCR 0x20
|
|
#define SCOOP_GPWR 0x24
|
|
#define SCOOP_GPRR 0x28
|
|
|
|
static inline void scoop_gpio_handler_update(struct scoop_info_s *s) {
|
|
uint32_t level, diff;
|
|
int bit;
|
|
level = s->gpio_level & s->gpio_dir;
|
|
|
|
for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
|
|
bit = ffs(diff) - 1;
|
|
qemu_set_irq(s->handler[bit], (level >> bit) & 1);
|
|
}
|
|
|
|
s->prev_level = level;
|
|
}
|
|
|
|
static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr)
|
|
{
|
|
struct scoop_info_s *s = (struct scoop_info_s *) opaque;
|
|
addr -= s->target_base;
|
|
|
|
switch (addr) {
|
|
case SCOOP_MCR:
|
|
return s->mcr;
|
|
case SCOOP_CDR:
|
|
return s->cdr;
|
|
case SCOOP_CSR:
|
|
return s->status;
|
|
case SCOOP_CPR:
|
|
return s->power;
|
|
case SCOOP_CCR:
|
|
return s->ccr;
|
|
case SCOOP_IRR_IRM:
|
|
return s->irr;
|
|
case SCOOP_IMR:
|
|
return s->imr;
|
|
case SCOOP_ISR:
|
|
return s->isr;
|
|
case SCOOP_GPCR:
|
|
return s->gpio_dir;
|
|
case SCOOP_GPWR:
|
|
return s->gpio_level;
|
|
case SCOOP_GPRR:
|
|
return s->gprr;
|
|
default:
|
|
spitz_printf("Bad register offset " REG_FMT "\n", addr);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
|
|
{
|
|
struct scoop_info_s *s = (struct scoop_info_s *) opaque;
|
|
addr -= s->target_base;
|
|
value &= 0xffff;
|
|
|
|
switch (addr) {
|
|
case SCOOP_MCR:
|
|
s->mcr = value;
|
|
break;
|
|
case SCOOP_CDR:
|
|
s->cdr = value;
|
|
break;
|
|
case SCOOP_CPR:
|
|
s->power = value;
|
|
if (value & 0x80)
|
|
s->power |= 0x8040;
|
|
break;
|
|
case SCOOP_CCR:
|
|
s->ccr = value;
|
|
break;
|
|
case SCOOP_IRR_IRM:
|
|
s->irr = value;
|
|
break;
|
|
case SCOOP_IMR:
|
|
s->imr = value;
|
|
break;
|
|
case SCOOP_ISR:
|
|
s->isr = value;
|
|
break;
|
|
case SCOOP_GPCR:
|
|
s->gpio_dir = value;
|
|
scoop_gpio_handler_update(s);
|
|
break;
|
|
case SCOOP_GPWR:
|
|
s->gpio_level = value & s->gpio_dir;
|
|
scoop_gpio_handler_update(s);
|
|
break;
|
|
case SCOOP_GPRR:
|
|
s->gprr = value;
|
|
break;
|
|
default:
|
|
spitz_printf("Bad register offset " REG_FMT "\n", addr);
|
|
}
|
|
}
|
|
|
|
CPUReadMemoryFunc *scoop_readfn[] = {
|
|
scoop_readb,
|
|
scoop_readb,
|
|
scoop_readb,
|
|
};
|
|
CPUWriteMemoryFunc *scoop_writefn[] = {
|
|
scoop_writeb,
|
|
scoop_writeb,
|
|
scoop_writeb,
|
|
};
|
|
|
|
static void scoop_gpio_set(void *opaque, int line, int level)
|
|
{
|
|
struct scoop_info_s *s = (struct scoop_info_s *) s;
|
|
|
|
if (level)
|
|
s->gpio_level |= (1 << line);
|
|
else
|
|
s->gpio_level &= ~(1 << line);
|
|
}
|
|
|
|
static inline qemu_irq *scoop_gpio_in_get(struct scoop_info_s *s)
|
|
{
|
|
return s->in;
|
|
}
|
|
|
|
static inline void scoop_gpio_out_set(struct scoop_info_s *s, int line,
|
|
qemu_irq handler) {
|
|
if (line >= 16) {
|
|
spitz_printf("No GPIO pin %i\n", line);
|
|
return;
|
|
}
|
|
|
|
s->handler[line] = handler;
|
|
}
|
|
|
|
static void scoop_save(QEMUFile *f, void *opaque)
|
|
{
|
|
struct scoop_info_s *s = (struct scoop_info_s *) opaque;
|
|
qemu_put_be16s(f, &s->status);
|
|
qemu_put_be16s(f, &s->power);
|
|
qemu_put_be32s(f, &s->gpio_level);
|
|
qemu_put_be32s(f, &s->gpio_dir);
|
|
qemu_put_be32s(f, &s->prev_level);
|
|
qemu_put_be16s(f, &s->mcr);
|
|
qemu_put_be16s(f, &s->cdr);
|
|
qemu_put_be16s(f, &s->ccr);
|
|
qemu_put_be16s(f, &s->irr);
|
|
qemu_put_be16s(f, &s->imr);
|
|
qemu_put_be16s(f, &s->isr);
|
|
qemu_put_be16s(f, &s->gprr);
|
|
}
|
|
|
|
static int scoop_load(QEMUFile *f, void *opaque, int version_id)
|
|
{
|
|
struct scoop_info_s *s = (struct scoop_info_s *) opaque;
|
|
qemu_get_be16s(f, &s->status);
|
|
qemu_get_be16s(f, &s->power);
|
|
qemu_get_be32s(f, &s->gpio_level);
|
|
qemu_get_be32s(f, &s->gpio_dir);
|
|
qemu_get_be32s(f, &s->prev_level);
|
|
qemu_get_be16s(f, &s->mcr);
|
|
qemu_get_be16s(f, &s->cdr);
|
|
qemu_get_be16s(f, &s->ccr);
|
|
qemu_get_be16s(f, &s->irr);
|
|
qemu_get_be16s(f, &s->imr);
|
|
qemu_get_be16s(f, &s->isr);
|
|
qemu_get_be16s(f, &s->gprr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct scoop_info_s *spitz_scoop_init(struct pxa2xx_state_s *cpu,
|
|
int count) {
|
|
int iomemtype;
|
|
struct scoop_info_s *s;
|
|
|
|
s = (struct scoop_info_s *)
|
|
qemu_mallocz(sizeof(struct scoop_info_s) * 2);
|
|
memset(s, 0, sizeof(struct scoop_info_s) * count);
|
|
s[0].target_base = 0x10800000;
|
|
s[1].target_base = 0x08800040;
|
|
|
|
/* Ready */
|
|
s[0].status = 0x02;
|
|
s[1].status = 0x02;
|
|
|
|
s[0].in = qemu_allocate_irqs(scoop_gpio_set, &s[0], 16);
|
|
iomemtype = cpu_register_io_memory(0, scoop_readfn,
|
|
scoop_writefn, &s[0]);
|
|
cpu_register_physical_memory(s[0].target_base, 0x1000, iomemtype);
|
|
register_savevm("scoop", 0, 0, scoop_save, scoop_load, &s[0]);
|
|
|
|
if (count < 2)
|
|
return s;
|
|
|
|
s[1].in = qemu_allocate_irqs(scoop_gpio_set, &s[1], 16);
|
|
iomemtype = cpu_register_io_memory(0, scoop_readfn,
|
|
scoop_writefn, &s[1]);
|
|
cpu_register_physical_memory(s[1].target_base, 0x1000, iomemtype);
|
|
register_savevm("scoop", 1, 0, scoop_save, scoop_load, &s[1]);
|
|
|
|
return s;
|
|
}
|
|
|
|
/* LCD backlight controller */
|
|
|
|
#define LCDTG_RESCTL 0x00
|
|
#define LCDTG_PHACTRL 0x01
|
|
#define LCDTG_DUTYCTRL 0x02
|
|
#define LCDTG_POWERREG0 0x03
|
|
#define LCDTG_POWERREG1 0x04
|
|
#define LCDTG_GPOR3 0x05
|
|
#define LCDTG_PICTRL 0x06
|
|
#define LCDTG_POLCTRL 0x07
|
|
|
|
static int bl_intensity, bl_power;
|
|
|
|
static void spitz_bl_update(struct pxa2xx_state_s *s)
|
|
{
|
|
if (bl_power && bl_intensity)
|
|
spitz_printf("LCD Backlight now at %i/63\n", bl_intensity);
|
|
else
|
|
spitz_printf("LCD Backlight now off\n");
|
|
}
|
|
|
|
static inline void spitz_bl_bit5(void *opaque, int line, int level)
|
|
{
|
|
int prev = bl_intensity;
|
|
|
|
if (level)
|
|
bl_intensity &= ~0x20;
|
|
else
|
|
bl_intensity |= 0x20;
|
|
|
|
if (bl_power && prev != bl_intensity)
|
|
spitz_bl_update((struct pxa2xx_state_s *) opaque);
|
|
}
|
|
|
|
static inline void spitz_bl_power(void *opaque, int line, int level)
|
|
{
|
|
bl_power = !!level;
|
|
spitz_bl_update((struct pxa2xx_state_s *) opaque);
|
|
}
|
|
|
|
static void spitz_lcdtg_dac_put(void *opaque, uint8_t cmd)
|
|
{
|
|
int addr, value;
|
|
addr = cmd >> 5;
|
|
value = cmd & 0x1f;
|
|
|
|
switch (addr) {
|
|
case LCDTG_RESCTL:
|
|
if (value)
|
|
spitz_printf("LCD in QVGA mode\n");
|
|
else
|
|
spitz_printf("LCD in VGA mode\n");
|
|
break;
|
|
|
|
case LCDTG_DUTYCTRL:
|
|
bl_intensity &= ~0x1f;
|
|
bl_intensity |= value;
|
|
if (bl_power)
|
|
spitz_bl_update((struct pxa2xx_state_s *) opaque);
|
|
break;
|
|
|
|
case LCDTG_POWERREG0:
|
|
/* Set common voltage to M62332FP */
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* SSP devices */
|
|
|
|
#define CORGI_SSP_PORT 2
|
|
|
|
#define SPITZ_GPIO_LCDCON_CS 53
|
|
#define SPITZ_GPIO_ADS7846_CS 14
|
|
#define SPITZ_GPIO_MAX1111_CS 20
|
|
#define SPITZ_GPIO_TP_INT 11
|
|
|
|
static int lcd_en, ads_en, max_en;
|
|
static struct max111x_s *max1111;
|
|
static struct ads7846_state_s *ads7846;
|
|
|
|
/* "Demux" the signal based on current chipselect */
|
|
static uint32_t corgi_ssp_read(void *opaque)
|
|
{
|
|
if (lcd_en)
|
|
return 0;
|
|
if (ads_en)
|
|
return ads7846_read(ads7846);
|
|
if (max_en)
|
|
return max111x_read(max1111);
|
|
return 0;
|
|
}
|
|
|
|
static void corgi_ssp_write(void *opaque, uint32_t value)
|
|
{
|
|
if (lcd_en)
|
|
spitz_lcdtg_dac_put(opaque, value);
|
|
if (ads_en)
|
|
ads7846_write(ads7846, value);
|
|
if (max_en)
|
|
max111x_write(max1111, value);
|
|
}
|
|
|
|
static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
|
|
{
|
|
switch (line) {
|
|
case 0:
|
|
lcd_en = !level;
|
|
break;
|
|
case 1:
|
|
ads_en = !level;
|
|
break;
|
|
case 2:
|
|
max_en = !level;
|
|
break;
|
|
}
|
|
}
|
|
|
|
#define MAX1111_BATT_VOLT 1
|
|
#define MAX1111_BATT_TEMP 2
|
|
#define MAX1111_ACIN_VOLT 3
|
|
|
|
#define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */
|
|
#define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */
|
|
#define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */
|
|
|
|
static void spitz_adc_temp_on(void *opaque, int line, int level)
|
|
{
|
|
if (!max1111)
|
|
return;
|
|
|
|
if (level)
|
|
max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
|
|
else
|
|
max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
|
|
}
|
|
|
|
static void spitz_ssp_save(QEMUFile *f, void *opaque)
|
|
{
|
|
qemu_put_be32(f, lcd_en);
|
|
qemu_put_be32(f, ads_en);
|
|
qemu_put_be32(f, max_en);
|
|
qemu_put_be32(f, bl_intensity);
|
|
qemu_put_be32(f, bl_power);
|
|
}
|
|
|
|
static int spitz_ssp_load(QEMUFile *f, void *opaque, int version_id)
|
|
{
|
|
lcd_en = qemu_get_be32(f);
|
|
ads_en = qemu_get_be32(f);
|
|
max_en = qemu_get_be32(f);
|
|
bl_intensity = qemu_get_be32(f);
|
|
bl_power = qemu_get_be32(f);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void spitz_ssp_attach(struct pxa2xx_state_s *cpu)
|
|
{
|
|
qemu_irq *chipselects;
|
|
|
|
lcd_en = ads_en = max_en = 0;
|
|
|
|
ads7846 = ads7846_init(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_TP_INT]);
|
|
|
|
max1111 = max1111_init(0);
|
|
max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
|
|
max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
|
|
max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
|
|
|
|
pxa2xx_ssp_attach(cpu->ssp[CORGI_SSP_PORT - 1], corgi_ssp_read,
|
|
corgi_ssp_write, cpu);
|
|
|
|
chipselects = qemu_allocate_irqs(corgi_ssp_gpio_cs, cpu, 3);
|
|
pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_LCDCON_CS, chipselects[0]);
|
|
pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ADS7846_CS, chipselects[1]);
|
|
pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_MAX1111_CS, chipselects[2]);
|
|
|
|
bl_intensity = 0x20;
|
|
bl_power = 0;
|
|
|
|
register_savevm("spitz_ssp", 0, 0, spitz_ssp_save, spitz_ssp_load, cpu);
|
|
}
|
|
|
|
/* CF Microdrive */
|
|
|
|
static void spitz_microdrive_attach(struct pxa2xx_state_s *cpu)
|
|
{
|
|
struct pcmcia_card_s *md;
|
|
int index;
|
|
BlockDriverState *bs;
|
|
|
|
index = drive_get_index(IF_IDE, 0, 0);
|
|
if (index == -1)
|
|
return;
|
|
bs = drives_table[index].bdrv;
|
|
if (bdrv_is_inserted(bs) && !bdrv_is_removable(bs)) {
|
|
md = dscm1xxxx_init(bs);
|
|
pxa2xx_pcmcia_attach(cpu->pcmcia[1], md);
|
|
}
|
|
}
|
|
|
|
/* Wm8750 and Max7310 on I2C */
|
|
|
|
#define AKITA_MAX_ADDR 0x18
|
|
#define SPITZ_WM_ADDRL 0x1b
|
|
#define SPITZ_WM_ADDRH 0x1a
|
|
|
|
#define SPITZ_GPIO_WM 5
|
|
|
|
#ifdef HAS_AUDIO
|
|
static void spitz_wm8750_addr(void *opaque, int line, int level)
|
|
{
|
|
i2c_slave *wm = (i2c_slave *) opaque;
|
|
if (level)
|
|
i2c_set_slave_address(wm, SPITZ_WM_ADDRH);
|
|
else
|
|
i2c_set_slave_address(wm, SPITZ_WM_ADDRL);
|
|
}
|
|
#endif
|
|
|
|
static void spitz_i2c_setup(struct pxa2xx_state_s *cpu)
|
|
{
|
|
/* Attach the CPU on one end of our I2C bus. */
|
|
i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
|
|
|
|
#ifdef HAS_AUDIO
|
|
AudioState *audio;
|
|
i2c_slave *wm;
|
|
|
|
audio = AUD_init();
|
|
if (!audio)
|
|
return;
|
|
/* Attach a WM8750 to the bus */
|
|
wm = wm8750_init(bus, audio);
|
|
|
|
spitz_wm8750_addr(wm, 0, 0);
|
|
pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_WM,
|
|
qemu_allocate_irqs(spitz_wm8750_addr, wm, 1)[0]);
|
|
/* .. and to the sound interface. */
|
|
cpu->i2s->opaque = wm;
|
|
cpu->i2s->codec_out = wm8750_dac_dat;
|
|
cpu->i2s->codec_in = wm8750_adc_dat;
|
|
wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s);
|
|
#endif
|
|
}
|
|
|
|
static void spitz_akita_i2c_setup(struct pxa2xx_state_s *cpu)
|
|
{
|
|
/* Attach a Max7310 to Akita I2C bus. */
|
|
i2c_set_slave_address(max7310_init(pxa2xx_i2c_bus(cpu->i2c[0])),
|
|
AKITA_MAX_ADDR);
|
|
}
|
|
|
|
/* Other peripherals */
|
|
|
|
static void spitz_out_switch(void *opaque, int line, int level)
|
|
{
|
|
switch (line) {
|
|
case 0:
|
|
spitz_printf("Charging %s.\n", level ? "off" : "on");
|
|
break;
|
|
case 1:
|
|
spitz_printf("Discharging %s.\n", level ? "on" : "off");
|
|
break;
|
|
case 2:
|
|
spitz_printf("Green LED %s.\n", level ? "on" : "off");
|
|
break;
|
|
case 3:
|
|
spitz_printf("Orange LED %s.\n", level ? "on" : "off");
|
|
break;
|
|
case 4:
|
|
spitz_bl_bit5(opaque, line, level);
|
|
break;
|
|
case 5:
|
|
spitz_bl_power(opaque, line, level);
|
|
break;
|
|
case 6:
|
|
spitz_adc_temp_on(opaque, line, level);
|
|
break;
|
|
}
|
|
}
|
|
|
|
#define SPITZ_SCP_LED_GREEN 1
|
|
#define SPITZ_SCP_JK_B 2
|
|
#define SPITZ_SCP_CHRG_ON 3
|
|
#define SPITZ_SCP_MUTE_L 4
|
|
#define SPITZ_SCP_MUTE_R 5
|
|
#define SPITZ_SCP_CF_POWER 6
|
|
#define SPITZ_SCP_LED_ORANGE 7
|
|
#define SPITZ_SCP_JK_A 8
|
|
#define SPITZ_SCP_ADC_TEMP_ON 9
|
|
#define SPITZ_SCP2_IR_ON 1
|
|
#define SPITZ_SCP2_AKIN_PULLUP 2
|
|
#define SPITZ_SCP2_BACKLIGHT_CONT 7
|
|
#define SPITZ_SCP2_BACKLIGHT_ON 8
|
|
#define SPITZ_SCP2_MIC_BIAS 9
|
|
|
|
static void spitz_scoop_gpio_setup(struct pxa2xx_state_s *cpu,
|
|
struct scoop_info_s *scp, int num)
|
|
{
|
|
qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
|
|
|
|
scoop_gpio_out_set(&scp[0], SPITZ_SCP_CHRG_ON, outsignals[0]);
|
|
scoop_gpio_out_set(&scp[0], SPITZ_SCP_JK_B, outsignals[1]);
|
|
scoop_gpio_out_set(&scp[0], SPITZ_SCP_LED_GREEN, outsignals[2]);
|
|
scoop_gpio_out_set(&scp[0], SPITZ_SCP_LED_ORANGE, outsignals[3]);
|
|
|
|
if (num >= 2) {
|
|
scoop_gpio_out_set(&scp[1], SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
|
|
scoop_gpio_out_set(&scp[1], SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
|
|
}
|
|
|
|
scoop_gpio_out_set(&scp[0], SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
|
|
}
|
|
|
|
#define SPITZ_GPIO_HSYNC 22
|
|
#define SPITZ_GPIO_SD_DETECT 9
|
|
#define SPITZ_GPIO_SD_WP 81
|
|
#define SPITZ_GPIO_ON_RESET 89
|
|
#define SPITZ_GPIO_BAT_COVER 90
|
|
#define SPITZ_GPIO_CF1_IRQ 105
|
|
#define SPITZ_GPIO_CF1_CD 94
|
|
#define SPITZ_GPIO_CF2_IRQ 106
|
|
#define SPITZ_GPIO_CF2_CD 93
|
|
|
|
static int spitz_hsync;
|
|
|
|
static void spitz_lcd_hsync_handler(void *opaque, int line, int level)
|
|
{
|
|
struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
|
|
qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_HSYNC], spitz_hsync);
|
|
spitz_hsync ^= 1;
|
|
}
|
|
|
|
static void spitz_gpio_setup(struct pxa2xx_state_s *cpu, int slots)
|
|
{
|
|
qemu_irq lcd_hsync;
|
|
/*
|
|
* Bad hack: We toggle the LCD hsync GPIO on every GPIO status
|
|
* read to satisfy broken guests that poll-wait for hsync.
|
|
* Simulating a real hsync event would be less practical and
|
|
* wouldn't guarantee that a guest ever exits the loop.
|
|
*/
|
|
spitz_hsync = 0;
|
|
lcd_hsync = qemu_allocate_irqs(spitz_lcd_hsync_handler, cpu, 1)[0];
|
|
pxa2xx_gpio_read_notifier(cpu->gpio, lcd_hsync);
|
|
pxa2xx_lcd_vsync_notifier(cpu->lcd, lcd_hsync);
|
|
|
|
/* MMC/SD host */
|
|
pxa2xx_mmci_handlers(cpu->mmc,
|
|
pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_WP],
|
|
pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_DETECT]);
|
|
|
|
/* Battery lock always closed */
|
|
qemu_irq_raise(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_BAT_COVER]);
|
|
|
|
/* Handle reset */
|
|
pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset);
|
|
|
|
/* PCMCIA signals: card's IRQ and Card-Detect */
|
|
if (slots >= 1)
|
|
pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
|
|
pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_IRQ],
|
|
pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_CD]);
|
|
if (slots >= 2)
|
|
pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1],
|
|
pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_IRQ],
|
|
pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_CD]);
|
|
|
|
/* Initialise the screen rotation related signals */
|
|
spitz_gpio_invert[3] = 0; /* Always open */
|
|
if (graphic_rotate) { /* Tablet mode */
|
|
spitz_gpio_invert[4] = 0;
|
|
} else { /* Portrait mode */
|
|
spitz_gpio_invert[4] = 1;
|
|
}
|
|
qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWA],
|
|
spitz_gpio_invert[3]);
|
|
qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWB],
|
|
spitz_gpio_invert[4]);
|
|
}
|
|
|
|
/* Write the bootloader parameters memory area. */
|
|
|
|
#define MAGIC_CHG(a, b, c, d) ((d << 24) | (c << 16) | (b << 8) | a)
|
|
|
|
struct __attribute__ ((__packed__)) sl_param_info {
|
|
uint32_t comadj_keyword;
|
|
int32_t comadj;
|
|
|
|
uint32_t uuid_keyword;
|
|
char uuid[16];
|
|
|
|
uint32_t touch_keyword;
|
|
int32_t touch_xp;
|
|
int32_t touch_yp;
|
|
int32_t touch_xd;
|
|
int32_t touch_yd;
|
|
|
|
uint32_t adadj_keyword;
|
|
int32_t adadj;
|
|
|
|
uint32_t phad_keyword;
|
|
int32_t phadadj;
|
|
} spitz_bootparam = {
|
|
.comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'),
|
|
.comadj = 125,
|
|
.uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'),
|
|
.uuid = { -1 },
|
|
.touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'),
|
|
.touch_xp = -1,
|
|
.adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'),
|
|
.adadj = -1,
|
|
.phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'),
|
|
.phadadj = 0x01,
|
|
};
|
|
|
|
static void sl_bootparam_write(uint32_t ptr)
|
|
{
|
|
memcpy(phys_ram_base + ptr, &spitz_bootparam,
|
|
sizeof(struct sl_param_info));
|
|
}
|
|
|
|
#define SL_PXA_PARAM_BASE 0xa0000a00
|
|
|
|
/* Board init. */
|
|
enum spitz_model_e { spitz, akita, borzoi, terrier };
|
|
|
|
#define SPITZ_RAM 0x04000000
|
|
#define SPITZ_ROM 0x00800000
|
|
|
|
static struct arm_boot_info spitz_binfo = {
|
|
.loader_start = PXA2XX_SDRAM_BASE,
|
|
.ram_size = 0x04000000,
|
|
};
|
|
|
|
static void spitz_common_init(int ram_size, int vga_ram_size,
|
|
DisplayState *ds, const char *kernel_filename,
|
|
const char *kernel_cmdline, const char *initrd_filename,
|
|
const char *cpu_model, enum spitz_model_e model, int arm_id)
|
|
{
|
|
struct pxa2xx_state_s *cpu;
|
|
struct scoop_info_s *scp;
|
|
|
|
if (!cpu_model)
|
|
cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
|
|
|
|
/* Setup CPU & memory */
|
|
if (ram_size < SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE) {
|
|
fprintf(stderr, "This platform requires %i bytes of memory\n",
|
|
SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE);
|
|
exit(1);
|
|
}
|
|
cpu = pxa270_init(spitz_binfo.ram_size, ds, cpu_model);
|
|
|
|
sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
|
|
|
|
cpu_register_physical_memory(0, SPITZ_ROM,
|
|
qemu_ram_alloc(SPITZ_ROM) | IO_MEM_ROM);
|
|
|
|
/* Setup peripherals */
|
|
spitz_keyboard_register(cpu);
|
|
|
|
spitz_ssp_attach(cpu);
|
|
|
|
scp = spitz_scoop_init(cpu, (model == akita) ? 1 : 2);
|
|
|
|
spitz_scoop_gpio_setup(cpu, scp, (model == akita) ? 1 : 2);
|
|
|
|
spitz_gpio_setup(cpu, (model == akita) ? 1 : 2);
|
|
|
|
spitz_i2c_setup(cpu);
|
|
|
|
if (model == akita)
|
|
spitz_akita_i2c_setup(cpu);
|
|
|
|
if (model == terrier)
|
|
/* A 6.0 GB microdrive is permanently sitting in CF slot 1. */
|
|
spitz_microdrive_attach(cpu);
|
|
else if (model != akita)
|
|
/* A 4.0 GB microdrive is permanently sitting in CF slot 1. */
|
|
spitz_microdrive_attach(cpu);
|
|
|
|
/* Setup initial (reset) machine state */
|
|
cpu->env->regs[15] = spitz_binfo.loader_start;
|
|
|
|
spitz_binfo.kernel_filename = kernel_filename;
|
|
spitz_binfo.kernel_cmdline = kernel_cmdline;
|
|
spitz_binfo.initrd_filename = initrd_filename;
|
|
spitz_binfo.board_id = arm_id;
|
|
arm_load_kernel(cpu->env, &spitz_binfo);
|
|
sl_bootparam_write(SL_PXA_PARAM_BASE - PXA2XX_SDRAM_BASE);
|
|
}
|
|
|
|
static void spitz_init(int ram_size, int vga_ram_size,
|
|
const char *boot_device, DisplayState *ds,
|
|
const char *kernel_filename, const char *kernel_cmdline,
|
|
const char *initrd_filename, const char *cpu_model)
|
|
{
|
|
spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
|
|
kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
|
|
}
|
|
|
|
static void borzoi_init(int ram_size, int vga_ram_size,
|
|
const char *boot_device, DisplayState *ds,
|
|
const char *kernel_filename, const char *kernel_cmdline,
|
|
const char *initrd_filename, const char *cpu_model)
|
|
{
|
|
spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
|
|
kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
|
|
}
|
|
|
|
static void akita_init(int ram_size, int vga_ram_size,
|
|
const char *boot_device, DisplayState *ds,
|
|
const char *kernel_filename, const char *kernel_cmdline,
|
|
const char *initrd_filename, const char *cpu_model)
|
|
{
|
|
spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
|
|
kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
|
|
}
|
|
|
|
static void terrier_init(int ram_size, int vga_ram_size,
|
|
const char *boot_device, DisplayState *ds,
|
|
const char *kernel_filename, const char *kernel_cmdline,
|
|
const char *initrd_filename, const char *cpu_model)
|
|
{
|
|
spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
|
|
kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f);
|
|
}
|
|
|
|
QEMUMachine akitapda_machine = {
|
|
"akita",
|
|
"Akita PDA (PXA270)",
|
|
akita_init,
|
|
SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE + RAMSIZE_FIXED,
|
|
};
|
|
|
|
QEMUMachine spitzpda_machine = {
|
|
"spitz",
|
|
"Spitz PDA (PXA270)",
|
|
spitz_init,
|
|
SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE + RAMSIZE_FIXED,
|
|
};
|
|
|
|
QEMUMachine borzoipda_machine = {
|
|
"borzoi",
|
|
"Borzoi PDA (PXA270)",
|
|
borzoi_init,
|
|
SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE + RAMSIZE_FIXED,
|
|
};
|
|
|
|
QEMUMachine terrierpda_machine = {
|
|
"terrier",
|
|
"Terrier PDA (PXA270)",
|
|
terrier_init,
|
|
SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE + RAMSIZE_FIXED,
|
|
};
|