The NPCM730 and NPCM750 SoCs have three timer modules each holding five timers and some shared registers (e.g. interrupt status). Each timer runs at 25 MHz divided by a prescaler, and counts down from a configurable initial value to zero. When zero is reached, the interrupt flag for the timer is set, and the timer is disabled (one-shot mode) or reloaded from its initial value (periodic mode). This implementation is sufficient to boot a Linux kernel configured for NPCM750. Note that the kernel does not seem to actually turn on the interrupts. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-4-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
544 lines
15 KiB
C
544 lines
15 KiB
C
/*
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* Nuvoton NPCM7xx Timer Controller
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/misc/npcm7xx_clk.h"
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#include "hw/timer/npcm7xx_timer.h"
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#include "migration/vmstate.h"
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#include "qemu/bitops.h"
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#include "qemu/error-report.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/timer.h"
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#include "qemu/units.h"
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#include "trace.h"
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/* 32-bit register indices. */
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enum NPCM7xxTimerRegisters {
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NPCM7XX_TIMER_TCSR0,
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NPCM7XX_TIMER_TCSR1,
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NPCM7XX_TIMER_TICR0,
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NPCM7XX_TIMER_TICR1,
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NPCM7XX_TIMER_TDR0,
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NPCM7XX_TIMER_TDR1,
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NPCM7XX_TIMER_TISR,
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NPCM7XX_TIMER_WTCR,
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NPCM7XX_TIMER_TCSR2,
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NPCM7XX_TIMER_TCSR3,
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NPCM7XX_TIMER_TICR2,
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NPCM7XX_TIMER_TICR3,
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NPCM7XX_TIMER_TDR2,
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NPCM7XX_TIMER_TDR3,
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NPCM7XX_TIMER_TCSR4 = 0x0040 / sizeof(uint32_t),
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NPCM7XX_TIMER_TICR4 = 0x0048 / sizeof(uint32_t),
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NPCM7XX_TIMER_TDR4 = 0x0050 / sizeof(uint32_t),
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NPCM7XX_TIMER_REGS_END,
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};
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/* Register field definitions. */
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#define NPCM7XX_TCSR_CEN BIT(30)
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#define NPCM7XX_TCSR_IE BIT(29)
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#define NPCM7XX_TCSR_PERIODIC BIT(27)
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#define NPCM7XX_TCSR_CRST BIT(26)
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#define NPCM7XX_TCSR_CACT BIT(25)
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#define NPCM7XX_TCSR_RSVD 0x01ffff00
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#define NPCM7XX_TCSR_PRESCALE_START 0
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#define NPCM7XX_TCSR_PRESCALE_LEN 8
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/*
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* Returns the index of timer in the tc->timer array. This can be used to
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* locate the registers that belong to this timer.
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*/
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static int npcm7xx_timer_index(NPCM7xxTimerCtrlState *tc, NPCM7xxTimer *timer)
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{
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int index = timer - tc->timer;
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g_assert(index >= 0 && index < NPCM7XX_TIMERS_PER_CTRL);
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return index;
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}
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/* Return the value by which to divide the reference clock rate. */
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static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr)
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{
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return extract32(tcsr, NPCM7XX_TCSR_PRESCALE_START,
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NPCM7XX_TCSR_PRESCALE_LEN) + 1;
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}
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/* Convert a timer cycle count to a time interval in nanoseconds. */
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static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
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{
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int64_t ns = count;
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ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;
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ns *= npcm7xx_tcsr_prescaler(t->tcsr);
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return ns;
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}
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/* Convert a time interval in nanoseconds to a timer cycle count. */
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static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
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{
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int64_t count;
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count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);
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count /= npcm7xx_tcsr_prescaler(t->tcsr);
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return count;
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}
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/*
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* Raise the interrupt line if there's a pending interrupt and interrupts are
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* enabled for this timer. If not, lower it.
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*/
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static void npcm7xx_timer_check_interrupt(NPCM7xxTimer *t)
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{
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NPCM7xxTimerCtrlState *tc = t->ctrl;
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int index = npcm7xx_timer_index(tc, t);
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bool pending = (t->tcsr & NPCM7XX_TCSR_IE) && (tc->tisr & BIT(index));
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qemu_set_irq(t->irq, pending);
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trace_npcm7xx_timer_irq(DEVICE(tc)->canonical_path, index, pending);
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}
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/* Start or resume the timer. */
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static void npcm7xx_timer_start(NPCM7xxTimer *t)
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{
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int64_t now;
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now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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t->expires_ns = now + t->remaining_ns;
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timer_mod(&t->qtimer, t->expires_ns);
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}
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/*
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* Called when the counter reaches zero. Sets the interrupt flag, and either
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* restarts or disables the timer.
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*/
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static void npcm7xx_timer_reached_zero(NPCM7xxTimer *t)
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{
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NPCM7xxTimerCtrlState *tc = t->ctrl;
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int index = npcm7xx_timer_index(tc, t);
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tc->tisr |= BIT(index);
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if (t->tcsr & NPCM7XX_TCSR_PERIODIC) {
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t->remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
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if (t->tcsr & NPCM7XX_TCSR_CEN) {
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npcm7xx_timer_start(t);
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}
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} else {
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t->tcsr &= ~(NPCM7XX_TCSR_CEN | NPCM7XX_TCSR_CACT);
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}
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npcm7xx_timer_check_interrupt(t);
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}
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/* Stop counting. Record the time remaining so we can continue later. */
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static void npcm7xx_timer_pause(NPCM7xxTimer *t)
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{
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int64_t now;
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timer_del(&t->qtimer);
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now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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t->remaining_ns = t->expires_ns - now;
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if (t->remaining_ns <= 0) {
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npcm7xx_timer_reached_zero(t);
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}
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}
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/*
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* Restart the timer from its initial value. If the timer was enabled and stays
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* enabled, adjust the QEMU timer according to the new count. If the timer is
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* transitioning from disabled to enabled, the caller is expected to start the
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* timer later.
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*/
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static void npcm7xx_timer_restart(NPCM7xxTimer *t, uint32_t old_tcsr)
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{
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t->remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
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if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
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npcm7xx_timer_start(t);
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}
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}
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/* Register read and write handlers */
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static uint32_t npcm7xx_timer_read_tdr(NPCM7xxTimer *t)
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{
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if (t->tcsr & NPCM7XX_TCSR_CEN) {
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int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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return npcm7xx_timer_ns_to_count(t, t->expires_ns - now);
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}
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return npcm7xx_timer_ns_to_count(t, t->remaining_ns);
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}
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static void npcm7xx_timer_write_tcsr(NPCM7xxTimer *t, uint32_t new_tcsr)
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{
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uint32_t old_tcsr = t->tcsr;
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uint32_t tdr;
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if (new_tcsr & NPCM7XX_TCSR_RSVD) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: reserved bits in 0x%08x ignored\n",
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__func__, new_tcsr);
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new_tcsr &= ~NPCM7XX_TCSR_RSVD;
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}
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if (new_tcsr & NPCM7XX_TCSR_CACT) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: read-only bits in 0x%08x ignored\n",
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__func__, new_tcsr);
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new_tcsr &= ~NPCM7XX_TCSR_CACT;
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}
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if ((new_tcsr & NPCM7XX_TCSR_CRST) && (new_tcsr & NPCM7XX_TCSR_CEN)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: both CRST and CEN set; ignoring CEN.\n",
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__func__);
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new_tcsr &= ~NPCM7XX_TCSR_CEN;
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}
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/* Calculate the value of TDR before potentially changing the prescaler. */
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tdr = npcm7xx_timer_read_tdr(t);
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t->tcsr = (t->tcsr & NPCM7XX_TCSR_CACT) | new_tcsr;
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if (npcm7xx_tcsr_prescaler(old_tcsr) != npcm7xx_tcsr_prescaler(new_tcsr)) {
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/* Recalculate time remaining based on the current TDR value. */
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t->remaining_ns = npcm7xx_timer_count_to_ns(t, tdr);
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if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
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npcm7xx_timer_start(t);
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}
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}
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if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_IE) {
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npcm7xx_timer_check_interrupt(t);
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}
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if (new_tcsr & NPCM7XX_TCSR_CRST) {
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npcm7xx_timer_restart(t, old_tcsr);
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t->tcsr &= ~NPCM7XX_TCSR_CRST;
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}
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if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_CEN) {
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if (new_tcsr & NPCM7XX_TCSR_CEN) {
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t->tcsr |= NPCM7XX_TCSR_CACT;
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npcm7xx_timer_start(t);
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} else {
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t->tcsr &= ~NPCM7XX_TCSR_CACT;
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npcm7xx_timer_pause(t);
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}
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}
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}
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static void npcm7xx_timer_write_ticr(NPCM7xxTimer *t, uint32_t new_ticr)
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{
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t->ticr = new_ticr;
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npcm7xx_timer_restart(t, t->tcsr);
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}
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static void npcm7xx_timer_write_tisr(NPCM7xxTimerCtrlState *s, uint32_t value)
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{
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int i;
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s->tisr &= ~value;
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for (i = 0; i < ARRAY_SIZE(s->timer); i++) {
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if (value & (1U << i)) {
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npcm7xx_timer_check_interrupt(&s->timer[i]);
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}
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}
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}
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static hwaddr npcm7xx_tcsr_index(hwaddr reg)
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{
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switch (reg) {
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case NPCM7XX_TIMER_TCSR0:
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return 0;
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case NPCM7XX_TIMER_TCSR1:
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return 1;
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case NPCM7XX_TIMER_TCSR2:
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return 2;
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case NPCM7XX_TIMER_TCSR3:
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return 3;
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case NPCM7XX_TIMER_TCSR4:
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return 4;
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default:
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g_assert_not_reached();
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}
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}
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static hwaddr npcm7xx_ticr_index(hwaddr reg)
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{
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switch (reg) {
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case NPCM7XX_TIMER_TICR0:
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return 0;
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case NPCM7XX_TIMER_TICR1:
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return 1;
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case NPCM7XX_TIMER_TICR2:
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return 2;
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case NPCM7XX_TIMER_TICR3:
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return 3;
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case NPCM7XX_TIMER_TICR4:
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return 4;
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default:
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g_assert_not_reached();
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}
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}
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static hwaddr npcm7xx_tdr_index(hwaddr reg)
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{
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switch (reg) {
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case NPCM7XX_TIMER_TDR0:
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return 0;
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case NPCM7XX_TIMER_TDR1:
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return 1;
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case NPCM7XX_TIMER_TDR2:
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return 2;
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case NPCM7XX_TIMER_TDR3:
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return 3;
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case NPCM7XX_TIMER_TDR4:
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return 4;
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default:
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g_assert_not_reached();
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}
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}
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static uint64_t npcm7xx_timer_read(void *opaque, hwaddr offset, unsigned size)
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{
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NPCM7xxTimerCtrlState *s = opaque;
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uint64_t value = 0;
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hwaddr reg;
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reg = offset / sizeof(uint32_t);
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switch (reg) {
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case NPCM7XX_TIMER_TCSR0:
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case NPCM7XX_TIMER_TCSR1:
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case NPCM7XX_TIMER_TCSR2:
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case NPCM7XX_TIMER_TCSR3:
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case NPCM7XX_TIMER_TCSR4:
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value = s->timer[npcm7xx_tcsr_index(reg)].tcsr;
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break;
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case NPCM7XX_TIMER_TICR0:
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case NPCM7XX_TIMER_TICR1:
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case NPCM7XX_TIMER_TICR2:
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case NPCM7XX_TIMER_TICR3:
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case NPCM7XX_TIMER_TICR4:
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value = s->timer[npcm7xx_ticr_index(reg)].ticr;
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break;
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case NPCM7XX_TIMER_TDR0:
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case NPCM7XX_TIMER_TDR1:
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case NPCM7XX_TIMER_TDR2:
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case NPCM7XX_TIMER_TDR3:
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case NPCM7XX_TIMER_TDR4:
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value = npcm7xx_timer_read_tdr(&s->timer[npcm7xx_tdr_index(reg)]);
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break;
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case NPCM7XX_TIMER_TISR:
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value = s->tisr;
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break;
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case NPCM7XX_TIMER_WTCR:
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value = s->wtcr;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: invalid offset 0x%04" HWADDR_PRIx "\n",
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__func__, offset);
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break;
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}
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trace_npcm7xx_timer_read(DEVICE(s)->canonical_path, offset, value);
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return value;
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}
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static void npcm7xx_timer_write(void *opaque, hwaddr offset,
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uint64_t v, unsigned size)
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{
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uint32_t reg = offset / sizeof(uint32_t);
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NPCM7xxTimerCtrlState *s = opaque;
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uint32_t value = v;
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trace_npcm7xx_timer_write(DEVICE(s)->canonical_path, offset, value);
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switch (reg) {
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case NPCM7XX_TIMER_TCSR0:
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case NPCM7XX_TIMER_TCSR1:
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case NPCM7XX_TIMER_TCSR2:
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case NPCM7XX_TIMER_TCSR3:
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case NPCM7XX_TIMER_TCSR4:
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npcm7xx_timer_write_tcsr(&s->timer[npcm7xx_tcsr_index(reg)], value);
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return;
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case NPCM7XX_TIMER_TICR0:
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case NPCM7XX_TIMER_TICR1:
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case NPCM7XX_TIMER_TICR2:
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case NPCM7XX_TIMER_TICR3:
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case NPCM7XX_TIMER_TICR4:
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npcm7xx_timer_write_ticr(&s->timer[npcm7xx_ticr_index(reg)], value);
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return;
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case NPCM7XX_TIMER_TDR0:
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case NPCM7XX_TIMER_TDR1:
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case NPCM7XX_TIMER_TDR2:
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case NPCM7XX_TIMER_TDR3:
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case NPCM7XX_TIMER_TDR4:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
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__func__, offset);
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return;
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case NPCM7XX_TIMER_TISR:
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npcm7xx_timer_write_tisr(s, value);
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return;
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case NPCM7XX_TIMER_WTCR:
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qemu_log_mask(LOG_UNIMP, "%s: WTCR write not implemented: 0x%08x\n",
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__func__, value);
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return;
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}
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: invalid offset 0x%04" HWADDR_PRIx "\n",
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__func__, offset);
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}
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static const struct MemoryRegionOps npcm7xx_timer_ops = {
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.read = npcm7xx_timer_read,
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.write = npcm7xx_timer_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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.unaligned = false,
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},
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};
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/* Called when the QEMU timer expires. */
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static void npcm7xx_timer_expired(void *opaque)
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{
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NPCM7xxTimer *t = opaque;
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if (t->tcsr & NPCM7XX_TCSR_CEN) {
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npcm7xx_timer_reached_zero(t);
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}
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}
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static void npcm7xx_timer_enter_reset(Object *obj, ResetType type)
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{
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NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
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int i;
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for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
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NPCM7xxTimer *t = &s->timer[i];
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timer_del(&t->qtimer);
|
|
t->expires_ns = 0;
|
|
t->remaining_ns = 0;
|
|
t->tcsr = 0x00000005;
|
|
t->ticr = 0x00000000;
|
|
}
|
|
|
|
s->tisr = 0x00000000;
|
|
s->wtcr = 0x00000400;
|
|
}
|
|
|
|
static void npcm7xx_timer_hold_reset(Object *obj)
|
|
{
|
|
NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
|
|
int i;
|
|
|
|
for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
|
|
qemu_irq_lower(s->timer[i].irq);
|
|
}
|
|
}
|
|
|
|
static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
|
|
SysBusDevice *sbd = &s->parent;
|
|
int i;
|
|
|
|
for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
|
|
NPCM7xxTimer *t = &s->timer[i];
|
|
t->ctrl = s;
|
|
timer_init_ns(&t->qtimer, QEMU_CLOCK_VIRTUAL, npcm7xx_timer_expired, t);
|
|
sysbus_init_irq(sbd, &t->irq);
|
|
}
|
|
|
|
memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
|
|
TYPE_NPCM7XX_TIMER, 4 * KiB);
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
|
}
|
|
|
|
static const VMStateDescription vmstate_npcm7xx_timer = {
|
|
.name = "npcm7xx-timer",
|
|
.version_id = 0,
|
|
.minimum_version_id = 0,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_TIMER(qtimer, NPCM7xxTimer),
|
|
VMSTATE_INT64(expires_ns, NPCM7xxTimer),
|
|
VMSTATE_INT64(remaining_ns, NPCM7xxTimer),
|
|
VMSTATE_UINT32(tcsr, NPCM7xxTimer),
|
|
VMSTATE_UINT32(ticr, NPCM7xxTimer),
|
|
VMSTATE_END_OF_LIST(),
|
|
},
|
|
};
|
|
|
|
static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
|
|
.name = "npcm7xx-timer-ctrl",
|
|
.version_id = 0,
|
|
.minimum_version_id = 0,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
|
|
VMSTATE_UINT32(wtcr, NPCM7xxTimerCtrlState),
|
|
VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
|
|
NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
|
|
NPCM7xxTimer),
|
|
VMSTATE_END_OF_LIST(),
|
|
},
|
|
};
|
|
|
|
static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
ResettableClass *rc = RESETTABLE_CLASS(klass);
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS);
|
|
|
|
dc->desc = "NPCM7xx Timer Controller";
|
|
dc->realize = npcm7xx_timer_realize;
|
|
dc->vmsd = &vmstate_npcm7xx_timer_ctrl;
|
|
rc->phases.enter = npcm7xx_timer_enter_reset;
|
|
rc->phases.hold = npcm7xx_timer_hold_reset;
|
|
}
|
|
|
|
static const TypeInfo npcm7xx_timer_info = {
|
|
.name = TYPE_NPCM7XX_TIMER,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(NPCM7xxTimerCtrlState),
|
|
.class_init = npcm7xx_timer_class_init,
|
|
};
|
|
|
|
static void npcm7xx_timer_register_type(void)
|
|
{
|
|
type_register_static(&npcm7xx_timer_info);
|
|
}
|
|
type_init(npcm7xx_timer_register_type);
|