The SDRAM controller is shared across almost all 405 and 440 embedded processors, with some slight differences such as the sizes supported for each memory bank. Rename only; no functional changes. Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6062 c046a42c-6fe2-441c-8c8c-71466251a162
63 lines
2.5 KiB
C
63 lines
2.5 KiB
C
/*
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* QEMU PowerPC 4xx emulation shared definitions
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#if !defined(PPC_4XX_H)
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#define PPC_4XX_H
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#include "pci.h"
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/* PowerPC 4xx core initialization */
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CPUState *ppc4xx_init (const char *cpu_model,
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clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
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uint32_t sysclk);
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typedef struct ppc4xx_mmio_t ppc4xx_mmio_t;
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int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
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target_phys_addr_t offset, uint32_t len,
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CPUReadMemoryFunc **mem_read,
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CPUWriteMemoryFunc **mem_write, void *opaque);
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ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base);
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/* PowerPC 4xx universal interrupt controller */
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enum {
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PPCUIC_OUTPUT_INT = 0,
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PPCUIC_OUTPUT_CINT = 1,
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PPCUIC_OUTPUT_NB,
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};
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qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
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uint32_t dcr_base, int has_ssr, int has_vr);
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void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
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target_phys_addr_t *ram_bases,
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target_phys_addr_t *ram_sizes,
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int do_init);
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PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
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target_phys_addr_t config_space,
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target_phys_addr_t int_ack,
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target_phys_addr_t special_cycle,
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target_phys_addr_t registers);
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#endif /* !defined(PPC_4XX_H) */
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