It is a common thing amongst the various cpu reset functions want to flush the SoftMMU's TLB entries. This is done either by calling tlb_flush directly or by way of a general memset of the CPU structure (sometimes both). This moves the tlb_flush call to the common reset function and additionally ensures it is only done for the CONFIG_SOFTMMU case and when tcg is enabled. In some target cases we add an empty end_of_reset_fields structure to the target vCPU structure so have a clear end point for any memset which is resetting value in the structure before CPU_COMMON (where the TLB structures are). While this is a nice clean-up in general it is also a precursor for changes coming to cputlb for MTTCG where the clearing of entries can't be done arbitrarily across vCPUs. Currently the cpu_reset function is usually called from the context of another vCPU as the architectural power up sequence is run. By using the cputlb API functions we can ensure the right behaviour in the future. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
415 lines
11 KiB
C
415 lines
11 KiB
C
/*
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* OpenRISC virtual CPU header.
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*
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* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef OPENRISC_CPU_H
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#define OPENRISC_CPU_H
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#define TARGET_LONG_BITS 32
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#define CPUArchState struct CPUOpenRISCState
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/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
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struct OpenRISCCPU;
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#include "qemu-common.h"
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#include "exec/cpu-defs.h"
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#include "fpu/softfloat.h"
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#include "qom/cpu.h"
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#define TYPE_OPENRISC_CPU "or32-cpu"
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#define OPENRISC_CPU_CLASS(klass) \
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OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
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#define OPENRISC_CPU(obj) \
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OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
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#define OPENRISC_CPU_GET_CLASS(obj) \
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OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)
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/**
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* OpenRISCCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_reset: The parent class' reset handler.
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*
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* A OpenRISC CPU model.
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*/
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typedef struct OpenRISCCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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void (*parent_reset)(CPUState *cpu);
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} OpenRISCCPUClass;
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#define NB_MMU_MODES 3
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enum {
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MMU_NOMMU_IDX = 0,
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MMU_SUPERVISOR_IDX = 1,
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MMU_USER_IDX = 2,
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};
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#define TARGET_PAGE_BITS 13
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#define TARGET_PHYS_ADDR_SPACE_BITS 32
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#define TARGET_VIRT_ADDR_SPACE_BITS 32
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#define SET_FP_CAUSE(reg, v) do {\
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(reg) = ((reg) & ~(0x3f << 12)) | \
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((v & 0x3f) << 12);\
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} while (0)
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#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
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#define UPDATE_FP_FLAGS(reg, v) do {\
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(reg) |= ((v & 0x1f) << 2);\
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} while (0)
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/* Version Register */
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#define SPR_VR 0xFFFF003F
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/* Internal flags, delay slot flag */
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#define D_FLAG 1
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/* Interrupt */
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#define NR_IRQS 32
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/* Unit presece register */
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enum {
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UPR_UP = (1 << 0),
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UPR_DCP = (1 << 1),
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UPR_ICP = (1 << 2),
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UPR_DMP = (1 << 3),
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UPR_IMP = (1 << 4),
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UPR_MP = (1 << 5),
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UPR_DUP = (1 << 6),
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UPR_PCUR = (1 << 7),
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UPR_PMP = (1 << 8),
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UPR_PICP = (1 << 9),
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UPR_TTP = (1 << 10),
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UPR_CUP = (255 << 24),
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};
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/* CPU configure register */
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enum {
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CPUCFGR_NSGF = (15 << 0),
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CPUCFGR_CGF = (1 << 4),
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CPUCFGR_OB32S = (1 << 5),
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CPUCFGR_OB64S = (1 << 6),
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CPUCFGR_OF32S = (1 << 7),
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CPUCFGR_OF64S = (1 << 8),
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CPUCFGR_OV64S = (1 << 9),
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};
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/* DMMU configure register */
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enum {
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DMMUCFGR_NTW = (3 << 0),
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DMMUCFGR_NTS = (7 << 2),
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DMMUCFGR_NAE = (7 << 5),
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DMMUCFGR_CRI = (1 << 8),
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DMMUCFGR_PRI = (1 << 9),
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DMMUCFGR_TEIRI = (1 << 10),
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DMMUCFGR_HTR = (1 << 11),
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};
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/* IMMU configure register */
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enum {
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IMMUCFGR_NTW = (3 << 0),
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IMMUCFGR_NTS = (7 << 2),
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IMMUCFGR_NAE = (7 << 5),
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IMMUCFGR_CRI = (1 << 8),
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IMMUCFGR_PRI = (1 << 9),
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IMMUCFGR_TEIRI = (1 << 10),
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IMMUCFGR_HTR = (1 << 11),
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};
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/* Float point control status register */
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enum {
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FPCSR_FPEE = 1,
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FPCSR_RM = (3 << 1),
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FPCSR_OVF = (1 << 3),
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FPCSR_UNF = (1 << 4),
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FPCSR_SNF = (1 << 5),
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FPCSR_QNF = (1 << 6),
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FPCSR_ZF = (1 << 7),
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FPCSR_IXF = (1 << 8),
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FPCSR_IVF = (1 << 9),
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FPCSR_INF = (1 << 10),
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FPCSR_DZF = (1 << 11),
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};
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/* Exceptions indices */
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enum {
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EXCP_RESET = 0x1,
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EXCP_BUSERR = 0x2,
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EXCP_DPF = 0x3,
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EXCP_IPF = 0x4,
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EXCP_TICK = 0x5,
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EXCP_ALIGN = 0x6,
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EXCP_ILLEGAL = 0x7,
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EXCP_INT = 0x8,
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EXCP_DTLBMISS = 0x9,
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EXCP_ITLBMISS = 0xa,
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EXCP_RANGE = 0xb,
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EXCP_SYSCALL = 0xc,
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EXCP_FPE = 0xd,
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EXCP_TRAP = 0xe,
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EXCP_NR,
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};
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/* Supervisor register */
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enum {
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SR_SM = (1 << 0),
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SR_TEE = (1 << 1),
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SR_IEE = (1 << 2),
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SR_DCE = (1 << 3),
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SR_ICE = (1 << 4),
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SR_DME = (1 << 5),
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SR_IME = (1 << 6),
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SR_LEE = (1 << 7),
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SR_CE = (1 << 8),
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SR_F = (1 << 9),
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SR_CY = (1 << 10),
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SR_OV = (1 << 11),
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SR_OVE = (1 << 12),
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SR_DSX = (1 << 13),
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SR_EPH = (1 << 14),
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SR_FO = (1 << 15),
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SR_SUMRA = (1 << 16),
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SR_SCE = (1 << 17),
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};
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/* OpenRISC Hardware Capabilities */
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enum {
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OPENRISC_FEATURE_NSGF = (15 << 0),
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OPENRISC_FEATURE_CGF = (1 << 4),
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OPENRISC_FEATURE_OB32S = (1 << 5),
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OPENRISC_FEATURE_OB64S = (1 << 6),
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OPENRISC_FEATURE_OF32S = (1 << 7),
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OPENRISC_FEATURE_OF64S = (1 << 8),
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OPENRISC_FEATURE_OV64S = (1 << 9),
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};
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/* Tick Timer Mode Register */
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enum {
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TTMR_TP = (0xfffffff),
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TTMR_IP = (1 << 28),
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TTMR_IE = (1 << 29),
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TTMR_M = (3 << 30),
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};
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/* Timer Mode */
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enum {
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TIMER_NONE = (0 << 30),
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TIMER_INTR = (1 << 30),
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TIMER_SHOT = (2 << 30),
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TIMER_CONT = (3 << 30),
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};
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/* TLB size */
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enum {
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DTLB_WAYS = 1,
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DTLB_SIZE = 64,
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DTLB_MASK = (DTLB_SIZE-1),
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ITLB_WAYS = 1,
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ITLB_SIZE = 64,
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ITLB_MASK = (ITLB_SIZE-1),
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};
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/* TLB prot */
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enum {
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URE = (1 << 6),
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UWE = (1 << 7),
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SRE = (1 << 8),
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SWE = (1 << 9),
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SXE = (1 << 6),
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UXE = (1 << 7),
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};
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/* check if tlb available */
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enum {
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TLBRET_INVALID = -3,
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TLBRET_NOMATCH = -2,
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TLBRET_BADADDR = -1,
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TLBRET_MATCH = 0
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};
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typedef struct OpenRISCTLBEntry {
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uint32_t mr;
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uint32_t tr;
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} OpenRISCTLBEntry;
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#ifndef CONFIG_USER_ONLY
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typedef struct CPUOpenRISCTLBContext {
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OpenRISCTLBEntry itlb[ITLB_WAYS][ITLB_SIZE];
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OpenRISCTLBEntry dtlb[DTLB_WAYS][DTLB_SIZE];
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int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu,
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hwaddr *physical,
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int *prot,
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target_ulong address, int rw);
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int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu,
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hwaddr *physical,
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int *prot,
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target_ulong address, int rw);
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} CPUOpenRISCTLBContext;
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#endif
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typedef struct CPUOpenRISCState {
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target_ulong gpr[32]; /* General registers */
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target_ulong pc; /* Program counter */
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target_ulong npc; /* Next PC */
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target_ulong ppc; /* Prev PC */
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target_ulong jmp_pc; /* Jump PC */
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target_ulong machi; /* Multiply register MACHI */
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target_ulong maclo; /* Multiply register MACLO */
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target_ulong fpmaddhi; /* Multiply and add float register FPMADDHI */
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target_ulong fpmaddlo; /* Multiply and add float register FPMADDLO */
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target_ulong epcr; /* Exception PC register */
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target_ulong eear; /* Exception EA register */
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uint32_t sr; /* Supervisor register */
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uint32_t vr; /* Version register */
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uint32_t upr; /* Unit presence register */
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uint32_t cpucfgr; /* CPU configure register */
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uint32_t dmmucfgr; /* DMMU configure register */
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uint32_t immucfgr; /* IMMU configure register */
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uint32_t esr; /* Exception supervisor register */
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uint32_t fpcsr; /* Float register */
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float_status fp_status;
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uint32_t flags; /* cpu_flags, we only use it for exception
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in solt so far. */
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uint32_t btaken; /* the SR_F bit */
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/* Fields up to this point are cleared by a CPU reset */
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struct {} end_reset_fields;
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CPU_COMMON
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/* Fields from here on are preserved across CPU reset. */
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#ifndef CONFIG_USER_ONLY
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CPUOpenRISCTLBContext * tlb;
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QEMUTimer *timer;
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uint32_t ttmr; /* Timer tick mode register */
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uint32_t ttcr; /* Timer tick count register */
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uint32_t picmr; /* Interrupt mask register */
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uint32_t picsr; /* Interrupt contrl register*/
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#endif
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void *irq[32]; /* Interrupt irq input */
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} CPUOpenRISCState;
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/**
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* OpenRISCCPU:
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* @env: #CPUOpenRISCState
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*
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* A OpenRISC CPU.
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*/
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typedef struct OpenRISCCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUOpenRISCState env;
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uint32_t feature; /* CPU Capabilities */
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} OpenRISCCPU;
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static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env)
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{
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return container_of(env, OpenRISCCPU, env);
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}
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#define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))
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#define ENV_OFFSET offsetof(OpenRISCCPU, env)
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OpenRISCCPU *cpu_openrisc_init(const char *cpu_model);
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void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
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void openrisc_cpu_do_interrupt(CPUState *cpu);
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bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
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void openrisc_cpu_dump_state(CPUState *cpu, FILE *f,
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fprintf_function cpu_fprintf, int flags);
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hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
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int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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void openrisc_translate_init(void);
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int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address,
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int rw, int mmu_idx);
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int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc);
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#define cpu_list cpu_openrisc_list
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#define cpu_signal_handler cpu_openrisc_signal_handler
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#ifndef CONFIG_USER_ONLY
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extern const struct VMStateDescription vmstate_openrisc_cpu;
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/* hw/openrisc_pic.c */
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void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
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/* hw/openrisc_timer.c */
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void cpu_openrisc_clock_init(OpenRISCCPU *cpu);
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void cpu_openrisc_count_update(OpenRISCCPU *cpu);
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void cpu_openrisc_timer_update(OpenRISCCPU *cpu);
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void cpu_openrisc_count_start(OpenRISCCPU *cpu);
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void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
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void cpu_openrisc_mmu_init(OpenRISCCPU *cpu);
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int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
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hwaddr *physical,
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int *prot, target_ulong address, int rw);
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int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
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hwaddr *physical,
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int *prot, target_ulong address, int rw);
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int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
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hwaddr *physical,
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int *prot, target_ulong address, int rw);
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#endif
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#define cpu_init(cpu_model) CPU(cpu_openrisc_init(cpu_model))
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#include "exec/cpu-all.h"
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static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
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target_ulong *pc,
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target_ulong *cs_base, uint32_t *flags)
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{
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*pc = env->pc;
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*cs_base = 0;
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/* D_FLAG -- branch instruction exception */
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*flags = (env->flags & D_FLAG);
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}
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static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch)
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{
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if (!(env->sr & SR_IME)) {
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return MMU_NOMMU_IDX;
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}
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return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX;
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}
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#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
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#endif /* OPENRISC_CPU_H */
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