Currently the ptimer design uses a QEMU bottom-half as its mechanism for calling back into the device model using the ptimer when the timer has expired. Unfortunately this design is fatally flawed, because it means that there is a lag between the ptimer updating its own state and the device callback function updating device state, and guest accesses to device registers between the two can return inconsistent device state. We want to replace the bottom-half design with one where the guest device's callback is called either immediately (when the ptimer triggers by timeout) or when the device model code closes a transaction-begin/end section (when the ptimer triggers because the device model changed the ptimer's count value or other state). As the first step, rename ptimer_init() to ptimer_init_with_bh(), to free up the ptimer_init() name for the new API. We can then convert all the ptimer users away from ptimer_init_with_bh() before removing it entirely. (Commit created with git grep -l ptimer_init | xargs sed -i -e 's/ptimer_init/ptimer_init_with_bh/' and three overlong lines folded by hand.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191008171740.9679-2-peter.maydell@linaro.org
273 lines
7.9 KiB
C
273 lines
7.9 KiB
C
/*
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* ARM CMSDK APB timer emulation
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*
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* Copyright (c) 2017 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/* This is a model of the "APB timer" which is part of the Cortex-M
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* System Design Kit (CMSDK) and documented in the Cortex-M System
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* Design Kit Technical Reference Manual (ARM DDI0479C):
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* https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
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*
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* The hardware has an EXTIN input wire, which can be configured
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* by the guest to act either as a 'timer enable' (timer does not run
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* when EXTIN is low), or as a 'timer clock' (timer runs at frequency
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* of EXTIN clock, not PCLK frequency). We don't model this.
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*
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* The documentation is not very clear about the exact behaviour;
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* we choose to implement that the interrupt is triggered when
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* the counter goes from 1 to 0, that the counter then holds at 0
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* for one clock cycle before reloading from the RELOAD register,
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* and that if the RELOAD register is 0 this does not cause an
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* interrupt (as there is no further 1->0 transition).
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/main-loop.h"
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#include "qemu/module.h"
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#include "qapi/error.h"
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#include "trace.h"
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#include "hw/sysbus.h"
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#include "hw/irq.h"
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#include "hw/registerfields.h"
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#include "hw/timer/cmsdk-apb-timer.h"
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#include "migration/vmstate.h"
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REG32(CTRL, 0)
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FIELD(CTRL, EN, 0, 1)
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FIELD(CTRL, SELEXTEN, 1, 1)
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FIELD(CTRL, SELEXTCLK, 2, 1)
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FIELD(CTRL, IRQEN, 3, 1)
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REG32(VALUE, 4)
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REG32(RELOAD, 8)
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REG32(INTSTATUS, 0xc)
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FIELD(INTSTATUS, IRQ, 0, 1)
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REG32(PID4, 0xFD0)
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REG32(PID5, 0xFD4)
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REG32(PID6, 0xFD8)
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REG32(PID7, 0xFDC)
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REG32(PID0, 0xFE0)
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REG32(PID1, 0xFE4)
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REG32(PID2, 0xFE8)
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REG32(PID3, 0xFEC)
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REG32(CID0, 0xFF0)
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REG32(CID1, 0xFF4)
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REG32(CID2, 0xFF8)
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REG32(CID3, 0xFFC)
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/* PID/CID values */
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static const int timer_id[] = {
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0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
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0x22, 0xb8, 0x1b, 0x00, /* PID0..PID3 */
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0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
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};
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static void cmsdk_apb_timer_update(CMSDKAPBTIMER *s)
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{
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qemu_set_irq(s->timerint, !!(s->intstatus & R_INTSTATUS_IRQ_MASK));
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}
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static uint64_t cmsdk_apb_timer_read(void *opaque, hwaddr offset, unsigned size)
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{
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CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque);
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uint64_t r;
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switch (offset) {
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case A_CTRL:
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r = s->ctrl;
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break;
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case A_VALUE:
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r = ptimer_get_count(s->timer);
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break;
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case A_RELOAD:
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r = ptimer_get_limit(s->timer);
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break;
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case A_INTSTATUS:
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r = s->intstatus;
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break;
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case A_PID4 ... A_CID3:
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r = timer_id[(offset - A_PID4) / 4];
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"CMSDK APB timer read: bad offset %x\n", (int) offset);
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r = 0;
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break;
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}
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trace_cmsdk_apb_timer_read(offset, r, size);
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return r;
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}
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static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque);
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trace_cmsdk_apb_timer_write(offset, value, size);
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switch (offset) {
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case A_CTRL:
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if (value & 6) {
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/* Bits [1] and [2] enable using EXTIN as either clock or
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* an enable line. We don't model this.
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*/
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qemu_log_mask(LOG_UNIMP,
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"CMSDK APB timer: EXTIN input not supported\n");
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}
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s->ctrl = value & 0xf;
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if (s->ctrl & R_CTRL_EN_MASK) {
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ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0);
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} else {
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ptimer_stop(s->timer);
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}
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break;
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case A_RELOAD:
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/* Writing to reload also sets the current timer value */
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if (!value) {
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ptimer_stop(s->timer);
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}
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ptimer_set_limit(s->timer, value, 1);
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if (value && (s->ctrl & R_CTRL_EN_MASK)) {
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/*
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* Make sure timer is running (it might have stopped if this
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* was an expired one-shot timer)
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*/
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ptimer_run(s->timer, 0);
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}
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break;
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case A_VALUE:
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if (!value && !ptimer_get_limit(s->timer)) {
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ptimer_stop(s->timer);
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}
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ptimer_set_count(s->timer, value);
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if (value && (s->ctrl & R_CTRL_EN_MASK)) {
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ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0);
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}
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break;
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case A_INTSTATUS:
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/* Just one bit, which is W1C. */
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value &= 1;
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s->intstatus &= ~value;
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cmsdk_apb_timer_update(s);
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break;
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case A_PID4 ... A_CID3:
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qemu_log_mask(LOG_GUEST_ERROR,
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"CMSDK APB timer write: write to RO offset 0x%x\n",
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(int)offset);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"CMSDK APB timer write: bad offset 0x%x\n", (int) offset);
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break;
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}
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}
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static const MemoryRegionOps cmsdk_apb_timer_ops = {
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.read = cmsdk_apb_timer_read,
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.write = cmsdk_apb_timer_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void cmsdk_apb_timer_tick(void *opaque)
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{
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CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque);
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if (s->ctrl & R_CTRL_IRQEN_MASK) {
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s->intstatus |= R_INTSTATUS_IRQ_MASK;
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cmsdk_apb_timer_update(s);
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}
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}
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static void cmsdk_apb_timer_reset(DeviceState *dev)
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{
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CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev);
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trace_cmsdk_apb_timer_reset();
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s->ctrl = 0;
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s->intstatus = 0;
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ptimer_stop(s->timer);
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/* Set the limit and the count */
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ptimer_set_limit(s->timer, 0, 1);
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}
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static void cmsdk_apb_timer_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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CMSDKAPBTIMER *s = CMSDK_APB_TIMER(obj);
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memory_region_init_io(&s->iomem, obj, &cmsdk_apb_timer_ops,
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s, "cmsdk-apb-timer", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->timerint);
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}
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static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
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{
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CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev);
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QEMUBH *bh;
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if (s->pclk_frq == 0) {
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error_setg(errp, "CMSDK APB timer: pclk-frq property must be set");
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return;
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}
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bh = qemu_bh_new(cmsdk_apb_timer_tick, s);
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s->timer = ptimer_init_with_bh(bh,
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PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
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PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT |
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PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
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PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
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ptimer_set_freq(s->timer, s->pclk_frq);
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}
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static const VMStateDescription cmsdk_apb_timer_vmstate = {
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.name = "cmsdk-apb-timer",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PTIMER(timer, CMSDKAPBTIMER),
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VMSTATE_UINT32(ctrl, CMSDKAPBTIMER),
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VMSTATE_UINT32(value, CMSDKAPBTIMER),
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VMSTATE_UINT32(reload, CMSDKAPBTIMER),
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VMSTATE_UINT32(intstatus, CMSDKAPBTIMER),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property cmsdk_apb_timer_properties[] = {
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DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTIMER, pclk_frq, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = cmsdk_apb_timer_realize;
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dc->vmsd = &cmsdk_apb_timer_vmstate;
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dc->reset = cmsdk_apb_timer_reset;
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dc->props = cmsdk_apb_timer_properties;
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}
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static const TypeInfo cmsdk_apb_timer_info = {
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.name = TYPE_CMSDK_APB_TIMER,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(CMSDKAPBTIMER),
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.instance_init = cmsdk_apb_timer_init,
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.class_init = cmsdk_apb_timer_class_init,
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};
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static void cmsdk_apb_timer_register_types(void)
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{
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type_register_static(&cmsdk_apb_timer_info);
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}
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type_init(cmsdk_apb_timer_register_types);
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