Currently the ptimer design uses a QEMU bottom-half as its mechanism for calling back into the device model using the ptimer when the timer has expired. Unfortunately this design is fatally flawed, because it means that there is a lag between the ptimer updating its own state and the device callback function updating device state, and guest accesses to device registers between the two can return inconsistent device state. We want to replace the bottom-half design with one where the guest device's callback is called either immediately (when the ptimer triggers by timeout) or when the device model code closes a transaction-begin/end section (when the ptimer triggers because the device model changed the ptimer's count value or other state). As the first step, rename ptimer_init() to ptimer_init_with_bh(), to free up the ptimer_init() name for the new API. We can then convert all the ptimer users away from ptimer_init_with_bh() before removing it entirely. (Commit created with git grep -l ptimer_init | xargs sed -i -e 's/ptimer_init/ptimer_init_with_bh/' and three overlong lines folded by hand.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191008171740.9679-2-peter.maydell@linaro.org
160 lines
3.9 KiB
C
160 lines
3.9 KiB
C
/*
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* OSTimer device simulation in PKUnity SoC
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*
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* Copyright (C) 2010-2012 Guan Xuetao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation, or any later version.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "hw/irq.h"
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#include "hw/ptimer.h"
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#include "qemu/main-loop.h"
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#include "qemu/module.h"
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#undef DEBUG_PUV3
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#include "hw/unicore32/puv3.h"
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#define TYPE_PUV3_OST "puv3_ost"
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#define PUV3_OST(obj) OBJECT_CHECK(PUV3OSTState, (obj), TYPE_PUV3_OST)
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/* puv3 ostimer implementation. */
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typedef struct PUV3OSTState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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QEMUBH *bh;
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qemu_irq irq;
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ptimer_state *ptimer;
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uint32_t reg_OSMR0;
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uint32_t reg_OSCR;
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uint32_t reg_OSSR;
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uint32_t reg_OIER;
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} PUV3OSTState;
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static uint64_t puv3_ost_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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PUV3OSTState *s = opaque;
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uint32_t ret = 0;
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switch (offset) {
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case 0x10: /* Counter Register */
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ret = s->reg_OSMR0 - (uint32_t)ptimer_get_count(s->ptimer);
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break;
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case 0x14: /* Status Register */
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ret = s->reg_OSSR;
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break;
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case 0x1c: /* Interrupt Enable Register */
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ret = s->reg_OIER;
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break;
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default:
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DPRINTF("Bad offset %x\n", (int)offset);
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}
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DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
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return ret;
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}
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static void puv3_ost_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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PUV3OSTState *s = opaque;
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DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
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switch (offset) {
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case 0x00: /* Match Register 0 */
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s->reg_OSMR0 = value;
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if (s->reg_OSMR0 > s->reg_OSCR) {
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ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR);
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} else {
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ptimer_set_count(s->ptimer, s->reg_OSMR0 +
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(0xffffffff - s->reg_OSCR));
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}
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ptimer_run(s->ptimer, 2);
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break;
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case 0x14: /* Status Register */
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assert(value == 0);
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if (s->reg_OSSR) {
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s->reg_OSSR = value;
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qemu_irq_lower(s->irq);
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}
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break;
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case 0x1c: /* Interrupt Enable Register */
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s->reg_OIER = value;
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break;
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default:
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DPRINTF("Bad offset %x\n", (int)offset);
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}
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}
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static const MemoryRegionOps puv3_ost_ops = {
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.read = puv3_ost_read,
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.write = puv3_ost_write,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void puv3_ost_tick(void *opaque)
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{
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PUV3OSTState *s = opaque;
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DPRINTF("ost hit when ptimer counter from 0x%x to 0x%x!\n",
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s->reg_OSCR, s->reg_OSMR0);
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s->reg_OSCR = s->reg_OSMR0;
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if (s->reg_OIER) {
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s->reg_OSSR = 1;
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qemu_irq_raise(s->irq);
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}
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}
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static void puv3_ost_realize(DeviceState *dev, Error **errp)
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{
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PUV3OSTState *s = PUV3_OST(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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s->reg_OIER = 0;
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s->reg_OSSR = 0;
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s->reg_OSMR0 = 0;
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s->reg_OSCR = 0;
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sysbus_init_irq(sbd, &s->irq);
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s->bh = qemu_bh_new(puv3_ost_tick, s);
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s->ptimer = ptimer_init_with_bh(s->bh, PTIMER_POLICY_DEFAULT);
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ptimer_set_freq(s->ptimer, 50 * 1000 * 1000);
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memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_ost",
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PUV3_REGS_OFFSET);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static void puv3_ost_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = puv3_ost_realize;
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}
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static const TypeInfo puv3_ost_info = {
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.name = TYPE_PUV3_OST,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(PUV3OSTState),
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.class_init = puv3_ost_class_init,
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};
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static void puv3_ost_register_type(void)
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{
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type_register_static(&puv3_ost_info);
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}
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type_init(puv3_ost_register_type)
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