Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-26-f4bug@amsat.org>
470 lines
17 KiB
C
470 lines
17 KiB
C
/*
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* Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* i.MX6 SOC emulation.
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*
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* Based on hw/arm/fsl-imx31.c
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "hw/arm/fsl-imx6.h"
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#include "sysemu/sysemu.h"
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#include "chardev/char.h"
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#include "qemu/error-report.h"
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#define IMX6_ESDHC_CAPABILITIES 0x057834b4
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#define NAME_SIZE 20
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static void fsl_imx6_init(Object *obj)
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{
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FslIMX6State *s = FSL_IMX6(obj);
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char name[NAME_SIZE];
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int i;
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if (smp_cpus > FSL_IMX6_NUM_CPUS) {
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error_report("%s: Only %d CPUs are supported (%d requested)",
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TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus);
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exit(1);
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}
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for (i = 0; i < smp_cpus; i++) {
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object_initialize(&s->cpu[i], sizeof(s->cpu[i]),
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"cortex-a9-" TYPE_ARM_CPU);
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snprintf(name, NAME_SIZE, "cpu%d", i);
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object_property_add_child(obj, name, OBJECT(&s->cpu[i]), NULL);
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}
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object_initialize(&s->a9mpcore, sizeof(s->a9mpcore), TYPE_A9MPCORE_PRIV);
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qdev_set_parent_bus(DEVICE(&s->a9mpcore), sysbus_get_default());
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object_property_add_child(obj, "a9mpcore", OBJECT(&s->a9mpcore), NULL);
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object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX6_CCM);
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qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default());
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object_property_add_child(obj, "ccm", OBJECT(&s->ccm), NULL);
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object_initialize(&s->src, sizeof(s->src), TYPE_IMX6_SRC);
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qdev_set_parent_bus(DEVICE(&s->src), sysbus_get_default());
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object_property_add_child(obj, "src", OBJECT(&s->src), NULL);
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for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
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object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL);
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qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
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snprintf(name, NAME_SIZE, "uart%d", i + 1);
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object_property_add_child(obj, name, OBJECT(&s->uart[i]), NULL);
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}
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object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX6_GPT);
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qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default());
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object_property_add_child(obj, "gpt", OBJECT(&s->gpt), NULL);
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for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
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object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT);
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qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default());
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snprintf(name, NAME_SIZE, "epit%d", i + 1);
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object_property_add_child(obj, name, OBJECT(&s->epit[i]), NULL);
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}
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for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
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object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);
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qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());
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snprintf(name, NAME_SIZE, "i2c%d", i + 1);
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object_property_add_child(obj, name, OBJECT(&s->i2c[i]), NULL);
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}
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for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
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object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO);
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qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default());
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snprintf(name, NAME_SIZE, "gpio%d", i + 1);
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object_property_add_child(obj, name, OBJECT(&s->gpio[i]), NULL);
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}
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for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
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object_initialize(&s->esdhc[i], sizeof(s->esdhc[i]), TYPE_IMX_USDHC);
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qdev_set_parent_bus(DEVICE(&s->esdhc[i]), sysbus_get_default());
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snprintf(name, NAME_SIZE, "sdhc%d", i + 1);
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object_property_add_child(obj, name, OBJECT(&s->esdhc[i]), NULL);
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}
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for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
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object_initialize(&s->spi[i], sizeof(s->spi[i]), TYPE_IMX_SPI);
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qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
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snprintf(name, NAME_SIZE, "spi%d", i + 1);
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object_property_add_child(obj, name, OBJECT(&s->spi[i]), NULL);
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}
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object_initialize(&s->eth, sizeof(s->eth), TYPE_IMX_ENET);
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qdev_set_parent_bus(DEVICE(&s->eth), sysbus_get_default());
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object_property_add_child(obj, "eth", OBJECT(&s->eth), NULL);
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}
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static void fsl_imx6_realize(DeviceState *dev, Error **errp)
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{
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FslIMX6State *s = FSL_IMX6(dev);
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uint16_t i;
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Error *err = NULL;
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for (i = 0; i < smp_cpus; i++) {
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/* On uniprocessor, the CBAR is set to 0 */
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if (smp_cpus > 1) {
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object_property_set_int(OBJECT(&s->cpu[i]), FSL_IMX6_A9MPCORE_ADDR,
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"reset-cbar", &error_abort);
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}
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/* All CPU but CPU 0 start in power off mode */
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if (i) {
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object_property_set_bool(OBJECT(&s->cpu[i]), true,
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"start-powered-off", &error_abort);
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}
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object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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}
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object_property_set_int(OBJECT(&s->a9mpcore), smp_cpus, "num-cpu",
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&error_abort);
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object_property_set_int(OBJECT(&s->a9mpcore),
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FSL_IMX6_MAX_IRQ + GIC_INTERNAL, "num-irq",
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&error_abort);
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object_property_set_bool(OBJECT(&s->a9mpcore), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR);
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for (i = 0; i < smp_cpus; i++) {
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
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qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus,
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qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
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}
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object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR);
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object_property_set_bool(OBJECT(&s->src), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR);
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/* Initialize all UARTs */
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for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
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static const struct {
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hwaddr addr;
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unsigned int irq;
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} serial_table[FSL_IMX6_NUM_UARTS] = {
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{ FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ },
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{ FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ },
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{ FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ },
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{ FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ },
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{ FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ },
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};
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if (i < MAX_SERIAL_PORTS) {
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Chardev *chr;
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chr = serial_hds[i];
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if (!chr) {
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char *label = g_strdup_printf("imx6.uart%d", i + 1);
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chr = qemu_chr_new(label, "null");
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g_free(label);
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serial_hds[i] = chr;
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}
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qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
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}
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object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
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qdev_get_gpio_in(DEVICE(&s->a9mpcore),
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serial_table[i].irq));
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}
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s->gpt.ccm = IMX_CCM(&s->ccm);
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object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
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qdev_get_gpio_in(DEVICE(&s->a9mpcore),
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FSL_IMX6_GPT_IRQ));
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/* Initialize all EPIT timers */
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for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
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static const struct {
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hwaddr addr;
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unsigned int irq;
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} epit_table[FSL_IMX6_NUM_EPITS] = {
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{ FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ },
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{ FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ },
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};
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s->epit[i].ccm = IMX_CCM(&s->ccm);
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object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
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qdev_get_gpio_in(DEVICE(&s->a9mpcore),
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epit_table[i].irq));
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}
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/* Initialize all I2C */
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for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
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static const struct {
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hwaddr addr;
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unsigned int irq;
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} i2c_table[FSL_IMX6_NUM_I2CS] = {
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{ FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ },
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{ FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ },
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{ FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ }
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};
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object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
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qdev_get_gpio_in(DEVICE(&s->a9mpcore),
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i2c_table[i].irq));
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}
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/* Initialize all GPIOs */
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for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
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static const struct {
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hwaddr addr;
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unsigned int irq_low;
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unsigned int irq_high;
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} gpio_table[FSL_IMX6_NUM_GPIOS] = {
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{
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FSL_IMX6_GPIO1_ADDR,
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FSL_IMX6_GPIO1_LOW_IRQ,
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FSL_IMX6_GPIO1_HIGH_IRQ
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},
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{
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FSL_IMX6_GPIO2_ADDR,
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FSL_IMX6_GPIO2_LOW_IRQ,
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FSL_IMX6_GPIO2_HIGH_IRQ
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},
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{
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FSL_IMX6_GPIO3_ADDR,
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FSL_IMX6_GPIO3_LOW_IRQ,
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FSL_IMX6_GPIO3_HIGH_IRQ
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},
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{
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FSL_IMX6_GPIO4_ADDR,
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FSL_IMX6_GPIO4_LOW_IRQ,
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FSL_IMX6_GPIO4_HIGH_IRQ
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},
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{
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FSL_IMX6_GPIO5_ADDR,
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FSL_IMX6_GPIO5_LOW_IRQ,
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FSL_IMX6_GPIO5_HIGH_IRQ
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},
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{
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FSL_IMX6_GPIO6_ADDR,
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FSL_IMX6_GPIO6_LOW_IRQ,
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FSL_IMX6_GPIO6_HIGH_IRQ
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},
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{
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FSL_IMX6_GPIO7_ADDR,
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FSL_IMX6_GPIO7_LOW_IRQ,
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FSL_IMX6_GPIO7_HIGH_IRQ
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},
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};
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object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-edge-sel",
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&error_abort);
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object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-upper-pin-irq",
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&error_abort);
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object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
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qdev_get_gpio_in(DEVICE(&s->a9mpcore),
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gpio_table[i].irq_low));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
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qdev_get_gpio_in(DEVICE(&s->a9mpcore),
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gpio_table[i].irq_high));
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}
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/* Initialize all SDHC */
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for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
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static const struct {
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hwaddr addr;
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unsigned int irq;
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} esdhc_table[FSL_IMX6_NUM_ESDHCS] = {
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{ FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ },
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{ FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ },
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{ FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ },
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{ FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ },
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};
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/* UHS-I SDIO3.0 SDR104 1.8V ADMA */
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object_property_set_uint(OBJECT(&s->esdhc[i]), 3, "sd-spec-version",
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&err);
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object_property_set_uint(OBJECT(&s->esdhc[i]), IMX6_ESDHC_CAPABILITIES,
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"capareg", &err);
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object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
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qdev_get_gpio_in(DEVICE(&s->a9mpcore),
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esdhc_table[i].irq));
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}
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/* Initialize all ECSPI */
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for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
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static const struct {
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hwaddr addr;
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unsigned int irq;
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} spi_table[FSL_IMX6_NUM_ECSPIS] = {
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{ FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ },
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{ FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ },
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{ FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ },
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{ FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ },
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{ FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ },
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};
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/* Initialize the SPI */
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object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
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qdev_get_gpio_in(DEVICE(&s->a9mpcore),
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spi_table[i].irq));
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}
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qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]);
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object_property_set_bool(OBJECT(&s->eth), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0,
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qdev_get_gpio_in(DEVICE(&s->a9mpcore),
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FSL_IMX6_ENET_MAC_IRQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1,
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qdev_get_gpio_in(DEVICE(&s->a9mpcore),
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FSL_IMX6_ENET_MAC_1588_IRQ));
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/* ROM memory */
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memory_region_init_rom(&s->rom, NULL, "imx6.rom",
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FSL_IMX6_ROM_SIZE, &err);
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|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR,
|
|
&s->rom);
|
|
|
|
/* CAAM memory */
|
|
memory_region_init_rom(&s->caam, NULL, "imx6.caam",
|
|
FSL_IMX6_CAAM_MEM_SIZE, &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR,
|
|
&s->caam);
|
|
|
|
/* OCRAM memory */
|
|
memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", FSL_IMX6_OCRAM_SIZE,
|
|
&err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR,
|
|
&s->ocram);
|
|
|
|
/* internal OCRAM (256 KB) is aliased over 1 MB */
|
|
memory_region_init_alias(&s->ocram_alias, NULL, "imx6.ocram_alias",
|
|
&s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE);
|
|
memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR,
|
|
&s->ocram_alias);
|
|
}
|
|
|
|
static void fsl_imx6_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
dc->realize = fsl_imx6_realize;
|
|
dc->desc = "i.MX6 SOC";
|
|
/* Reason: Uses serial_hds[] in the realize() function */
|
|
dc->user_creatable = false;
|
|
}
|
|
|
|
static const TypeInfo fsl_imx6_type_info = {
|
|
.name = TYPE_FSL_IMX6,
|
|
.parent = TYPE_DEVICE,
|
|
.instance_size = sizeof(FslIMX6State),
|
|
.instance_init = fsl_imx6_init,
|
|
.class_init = fsl_imx6_class_init,
|
|
};
|
|
|
|
static void fsl_imx6_register_types(void)
|
|
{
|
|
type_register_static(&fsl_imx6_type_info);
|
|
}
|
|
|
|
type_init(fsl_imx6_register_types)
|