It is the responsibility of board code for an armv7m system to set system_clock_scale appropriately for the CPU speed of the core. If it forgets to do this, then QEMU will hang if the guest tries to use the systick timer in the "tick at the CPU clock frequency" mode. We forgot that in a couple of our boards (see commitsce4f70e81e
,e7e5a9595a
). Add an assertion in the systick reset method so we don't let any new boards in with the same bug. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200825160847.18091-1-peter.maydell@linaro.org
271 lines
7.2 KiB
C
271 lines
7.2 KiB
C
/*
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* ARMv7M SysTick timer
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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* Copyright (c) 2017 Linaro Ltd
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* Written by Peter Maydell
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*
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* This code is licensed under the GPL (version 2 or later).
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*/
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#include "qemu/osdep.h"
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#include "hw/timer/armv7m_systick.h"
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#include "migration/vmstate.h"
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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#include "qemu/timer.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "trace.h"
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/* qemu timers run at 1GHz. We want something closer to 1MHz. */
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#define SYSTICK_SCALE 1000ULL
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#define SYSTICK_ENABLE (1 << 0)
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#define SYSTICK_TICKINT (1 << 1)
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#define SYSTICK_CLKSOURCE (1 << 2)
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#define SYSTICK_COUNTFLAG (1 << 16)
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int system_clock_scale;
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/* Conversion factor from qemu timer to SysTick frequencies. */
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static inline int64_t systick_scale(SysTickState *s)
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{
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if (s->control & SYSTICK_CLKSOURCE) {
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return system_clock_scale;
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} else {
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return 1000;
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}
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}
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static void systick_reload(SysTickState *s, int reset)
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{
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/* The Cortex-M3 Devices Generic User Guide says that "When the
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* ENABLE bit is set to 1, the counter loads the RELOAD value from the
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* SYST RVR register and then counts down". So, we need to check the
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* ENABLE bit before reloading the value.
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*/
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trace_systick_reload();
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if ((s->control & SYSTICK_ENABLE) == 0) {
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return;
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}
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if (reset) {
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s->tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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}
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s->tick += (s->reload + 1) * systick_scale(s);
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timer_mod(s->timer, s->tick);
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}
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static void systick_timer_tick(void *opaque)
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{
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SysTickState *s = (SysTickState *)opaque;
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trace_systick_timer_tick();
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s->control |= SYSTICK_COUNTFLAG;
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if (s->control & SYSTICK_TICKINT) {
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/* Tell the NVIC to pend the SysTick exception */
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qemu_irq_pulse(s->irq);
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}
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if (s->reload == 0) {
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s->control &= ~SYSTICK_ENABLE;
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} else {
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systick_reload(s, 0);
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}
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}
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static MemTxResult systick_read(void *opaque, hwaddr addr, uint64_t *data,
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unsigned size, MemTxAttrs attrs)
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{
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SysTickState *s = opaque;
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uint32_t val;
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if (attrs.user) {
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/* Generate BusFault for unprivileged accesses */
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return MEMTX_ERROR;
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}
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switch (addr) {
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case 0x0: /* SysTick Control and Status. */
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val = s->control;
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s->control &= ~SYSTICK_COUNTFLAG;
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break;
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case 0x4: /* SysTick Reload Value. */
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val = s->reload;
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break;
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case 0x8: /* SysTick Current Value. */
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{
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int64_t t;
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if ((s->control & SYSTICK_ENABLE) == 0) {
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val = 0;
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break;
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}
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t = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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if (t >= s->tick) {
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val = 0;
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break;
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}
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val = ((s->tick - (t + 1)) / systick_scale(s)) + 1;
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/* The interrupt in triggered when the timer reaches zero.
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However the counter is not reloaded until the next clock
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tick. This is a hack to return zero during the first tick. */
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if (val > s->reload) {
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val = 0;
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}
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break;
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}
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case 0xc: /* SysTick Calibration Value. */
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val = 10000;
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break;
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default:
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val = 0;
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qemu_log_mask(LOG_GUEST_ERROR,
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"SysTick: Bad read offset 0x%" HWADDR_PRIx "\n", addr);
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break;
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}
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trace_systick_read(addr, val, size);
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*data = val;
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return MEMTX_OK;
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}
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static MemTxResult systick_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size,
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MemTxAttrs attrs)
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{
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SysTickState *s = opaque;
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if (attrs.user) {
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/* Generate BusFault for unprivileged accesses */
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return MEMTX_ERROR;
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}
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trace_systick_write(addr, value, size);
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switch (addr) {
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case 0x0: /* SysTick Control and Status. */
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{
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uint32_t oldval = s->control;
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s->control &= 0xfffffff8;
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s->control |= value & 7;
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if ((oldval ^ value) & SYSTICK_ENABLE) {
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int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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if (value & SYSTICK_ENABLE) {
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if (s->tick) {
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s->tick += now;
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timer_mod(s->timer, s->tick);
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} else {
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systick_reload(s, 1);
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}
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} else {
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timer_del(s->timer);
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s->tick -= now;
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if (s->tick < 0) {
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s->tick = 0;
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}
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}
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} else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
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/* This is a hack. Force the timer to be reloaded
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when the reference clock is changed. */
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systick_reload(s, 1);
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}
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break;
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}
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case 0x4: /* SysTick Reload Value. */
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s->reload = value;
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break;
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case 0x8: /* SysTick Current Value. Writes reload the timer. */
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systick_reload(s, 1);
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s->control &= ~SYSTICK_COUNTFLAG;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"SysTick: Bad write offset 0x%" HWADDR_PRIx "\n", addr);
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}
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return MEMTX_OK;
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}
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static const MemoryRegionOps systick_ops = {
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.read_with_attrs = systick_read,
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.write_with_attrs = systick_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static void systick_reset(DeviceState *dev)
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{
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SysTickState *s = SYSTICK(dev);
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/*
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* Forgetting to set system_clock_scale is always a board code
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* bug. We can't check this earlier because for some boards
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* (like stellaris) it is not yet configured at the point where
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* the systick device is realized.
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*/
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assert(system_clock_scale != 0);
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s->control = 0;
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s->reload = 0;
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s->tick = 0;
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timer_del(s->timer);
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}
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static void systick_instance_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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SysTickState *s = SYSTICK(obj);
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memory_region_init_io(&s->iomem, obj, &systick_ops, s, "systick", 0xe0);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->irq);
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}
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static void systick_realize(DeviceState *dev, Error **errp)
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{
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SysTickState *s = SYSTICK(dev);
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s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
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}
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static const VMStateDescription vmstate_systick = {
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.name = "armv7m_systick",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(control, SysTickState),
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VMSTATE_UINT32(reload, SysTickState),
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VMSTATE_INT64(tick, SysTickState),
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VMSTATE_TIMER_PTR(timer, SysTickState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void systick_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &vmstate_systick;
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dc->reset = systick_reset;
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dc->realize = systick_realize;
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}
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static const TypeInfo armv7m_systick_info = {
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.name = TYPE_SYSTICK,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_init = systick_instance_init,
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.instance_size = sizeof(SysTickState),
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.class_init = systick_class_init,
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};
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static void armv7m_systick_register_types(void)
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{
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type_register_static(&armv7m_systick_info);
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}
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type_init(armv7m_systick_register_types)
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