Disabled in all TCG backends for now. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <20190116170114.26802-3-cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
1284 lines
42 KiB
C
1284 lines
42 KiB
C
/*
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* Common CPU TLB handling
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/main-loop.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/memory.h"
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#include "exec/address-spaces.h"
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#include "exec/cpu_ldst.h"
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#include "exec/cputlb.h"
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#include "exec/memory-internal.h"
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#include "exec/ram_addr.h"
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#include "tcg/tcg.h"
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#include "qemu/error-report.h"
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#include "exec/log.h"
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#include "exec/helper-proto.h"
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#include "qemu/atomic.h"
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#include "qemu/atomic128.h"
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/* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
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/* #define DEBUG_TLB */
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/* #define DEBUG_TLB_LOG */
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#ifdef DEBUG_TLB
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# define DEBUG_TLB_GATE 1
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# ifdef DEBUG_TLB_LOG
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# define DEBUG_TLB_LOG_GATE 1
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# else
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# define DEBUG_TLB_LOG_GATE 0
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# endif
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#else
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# define DEBUG_TLB_GATE 0
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# define DEBUG_TLB_LOG_GATE 0
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#endif
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#define tlb_debug(fmt, ...) do { \
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if (DEBUG_TLB_LOG_GATE) { \
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qemu_log_mask(CPU_LOG_MMU, "%s: " fmt, __func__, \
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## __VA_ARGS__); \
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} else if (DEBUG_TLB_GATE) { \
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fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \
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} \
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} while (0)
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#define assert_cpu_is_self(cpu) do { \
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if (DEBUG_TLB_GATE) { \
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g_assert(!(cpu)->created || qemu_cpu_is_self(cpu)); \
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} \
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} while (0)
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/* run_on_cpu_data.target_ptr should always be big enough for a
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* target_ulong even on 32 bit builds */
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QEMU_BUILD_BUG_ON(sizeof(target_ulong) > sizeof(run_on_cpu_data));
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/* We currently can't handle more than 16 bits in the MMUIDX bitmask.
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*/
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QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16);
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#define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1)
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#if TCG_TARGET_IMPLEMENTS_DYN_TLB
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static inline size_t sizeof_tlb(CPUArchState *env, uintptr_t mmu_idx)
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{
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return env->tlb_mask[mmu_idx] + (1 << CPU_TLB_ENTRY_BITS);
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}
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static void tlb_window_reset(CPUTLBWindow *window, int64_t ns,
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size_t max_entries)
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{
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window->begin_ns = ns;
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window->max_entries = max_entries;
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}
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static void tlb_dyn_init(CPUArchState *env)
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{
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int i;
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for (i = 0; i < NB_MMU_MODES; i++) {
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CPUTLBDesc *desc = &env->tlb_d[i];
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size_t n_entries = 1 << CPU_TLB_DYN_DEFAULT_BITS;
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tlb_window_reset(&desc->window, get_clock_realtime(), 0);
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desc->n_used_entries = 0;
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env->tlb_mask[i] = (n_entries - 1) << CPU_TLB_ENTRY_BITS;
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env->tlb_table[i] = g_new(CPUTLBEntry, n_entries);
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env->iotlb[i] = g_new(CPUIOTLBEntry, n_entries);
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}
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}
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/**
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* tlb_mmu_resize_locked() - perform TLB resize bookkeeping; resize if necessary
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* @env: CPU that owns the TLB
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* @mmu_idx: MMU index of the TLB
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*
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* Called with tlb_lock_held.
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*
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* We have two main constraints when resizing a TLB: (1) we only resize it
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* on a TLB flush (otherwise we'd have to take a perf hit by either rehashing
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* the array or unnecessarily flushing it), which means we do not control how
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* frequently the resizing can occur; (2) we don't have access to the guest's
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* future scheduling decisions, and therefore have to decide the magnitude of
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* the resize based on past observations.
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*
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* In general, a memory-hungry process can benefit greatly from an appropriately
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* sized TLB, since a guest TLB miss is very expensive. This doesn't mean that
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* we just have to make the TLB as large as possible; while an oversized TLB
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* results in minimal TLB miss rates, it also takes longer to be flushed
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* (flushes can be _very_ frequent), and the reduced locality can also hurt
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* performance.
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*
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* To achieve near-optimal performance for all kinds of workloads, we:
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*
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* 1. Aggressively increase the size of the TLB when the use rate of the
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* TLB being flushed is high, since it is likely that in the near future this
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* memory-hungry process will execute again, and its memory hungriness will
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* probably be similar.
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*
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* 2. Slowly reduce the size of the TLB as the use rate declines over a
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* reasonably large time window. The rationale is that if in such a time window
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* we have not observed a high TLB use rate, it is likely that we won't observe
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* it in the near future. In that case, once a time window expires we downsize
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* the TLB to match the maximum use rate observed in the window.
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*
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* 3. Try to keep the maximum use rate in a time window in the 30-70% range,
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* since in that range performance is likely near-optimal. Recall that the TLB
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* is direct mapped, so we want the use rate to be low (or at least not too
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* high), since otherwise we are likely to have a significant amount of
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* conflict misses.
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*/
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static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)
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{
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CPUTLBDesc *desc = &env->tlb_d[mmu_idx];
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size_t old_size = tlb_n_entries(env, mmu_idx);
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size_t rate;
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size_t new_size = old_size;
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int64_t now = get_clock_realtime();
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int64_t window_len_ms = 100;
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int64_t window_len_ns = window_len_ms * 1000 * 1000;
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bool window_expired = now > desc->window.begin_ns + window_len_ns;
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if (desc->n_used_entries > desc->window.max_entries) {
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desc->window.max_entries = desc->n_used_entries;
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}
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rate = desc->window.max_entries * 100 / old_size;
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if (rate > 70) {
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new_size = MIN(old_size << 1, 1 << CPU_TLB_DYN_MAX_BITS);
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} else if (rate < 30 && window_expired) {
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size_t ceil = pow2ceil(desc->window.max_entries);
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size_t expected_rate = desc->window.max_entries * 100 / ceil;
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/*
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* Avoid undersizing when the max number of entries seen is just below
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* a pow2. For instance, if max_entries == 1025, the expected use rate
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* would be 1025/2048==50%. However, if max_entries == 1023, we'd get
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* 1023/1024==99.9% use rate, so we'd likely end up doubling the size
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* later. Thus, make sure that the expected use rate remains below 70%.
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* (and since we double the size, that means the lowest rate we'd
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* expect to get is 35%, which is still in the 30-70% range where
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* we consider that the size is appropriate.)
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*/
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if (expected_rate > 70) {
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ceil *= 2;
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}
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new_size = MAX(ceil, 1 << CPU_TLB_DYN_MIN_BITS);
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}
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if (new_size == old_size) {
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if (window_expired) {
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tlb_window_reset(&desc->window, now, desc->n_used_entries);
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}
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return;
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}
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g_free(env->tlb_table[mmu_idx]);
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g_free(env->iotlb[mmu_idx]);
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tlb_window_reset(&desc->window, now, 0);
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/* desc->n_used_entries is cleared by the caller */
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env->tlb_mask[mmu_idx] = (new_size - 1) << CPU_TLB_ENTRY_BITS;
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env->tlb_table[mmu_idx] = g_try_new(CPUTLBEntry, new_size);
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env->iotlb[mmu_idx] = g_try_new(CPUIOTLBEntry, new_size);
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/*
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* If the allocations fail, try smaller sizes. We just freed some
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* memory, so going back to half of new_size has a good chance of working.
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* Increased memory pressure elsewhere in the system might cause the
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* allocations to fail though, so we progressively reduce the allocation
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* size, aborting if we cannot even allocate the smallest TLB we support.
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*/
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while (env->tlb_table[mmu_idx] == NULL || env->iotlb[mmu_idx] == NULL) {
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if (new_size == (1 << CPU_TLB_DYN_MIN_BITS)) {
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error_report("%s: %s", __func__, strerror(errno));
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abort();
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}
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new_size = MAX(new_size >> 1, 1 << CPU_TLB_DYN_MIN_BITS);
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env->tlb_mask[mmu_idx] = (new_size - 1) << CPU_TLB_ENTRY_BITS;
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g_free(env->tlb_table[mmu_idx]);
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g_free(env->iotlb[mmu_idx]);
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env->tlb_table[mmu_idx] = g_try_new(CPUTLBEntry, new_size);
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env->iotlb[mmu_idx] = g_try_new(CPUIOTLBEntry, new_size);
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}
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}
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static inline void tlb_table_flush_by_mmuidx(CPUArchState *env, int mmu_idx)
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{
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tlb_mmu_resize_locked(env, mmu_idx);
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memset(env->tlb_table[mmu_idx], -1, sizeof_tlb(env, mmu_idx));
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env->tlb_d[mmu_idx].n_used_entries = 0;
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}
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static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t mmu_idx)
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{
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env->tlb_d[mmu_idx].n_used_entries++;
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}
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static inline void tlb_n_used_entries_dec(CPUArchState *env, uintptr_t mmu_idx)
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{
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env->tlb_d[mmu_idx].n_used_entries--;
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}
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#else /* !TCG_TARGET_IMPLEMENTS_DYN_TLB */
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static inline void tlb_dyn_init(CPUArchState *env)
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{
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}
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static inline void tlb_table_flush_by_mmuidx(CPUArchState *env, int mmu_idx)
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{
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memset(env->tlb_table[mmu_idx], -1, sizeof(env->tlb_table[0]));
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}
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static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t mmu_idx)
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{
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}
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static inline void tlb_n_used_entries_dec(CPUArchState *env, uintptr_t mmu_idx)
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{
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}
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#endif /* TCG_TARGET_IMPLEMENTS_DYN_TLB */
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void tlb_init(CPUState *cpu)
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{
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CPUArchState *env = cpu->env_ptr;
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qemu_spin_init(&env->tlb_c.lock);
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/* Ensure that cpu_reset performs a full flush. */
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env->tlb_c.dirty = ALL_MMUIDX_BITS;
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tlb_dyn_init(env);
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}
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/* flush_all_helper: run fn across all cpus
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*
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* If the wait flag is set then the src cpu's helper will be queued as
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* "safe" work and the loop exited creating a synchronisation point
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* where all queued work will be finished before execution starts
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* again.
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*/
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static void flush_all_helper(CPUState *src, run_on_cpu_func fn,
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run_on_cpu_data d)
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{
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CPUState *cpu;
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CPU_FOREACH(cpu) {
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if (cpu != src) {
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async_run_on_cpu(cpu, fn, d);
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}
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}
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}
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void tlb_flush_counts(size_t *pfull, size_t *ppart, size_t *pelide)
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{
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CPUState *cpu;
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size_t full = 0, part = 0, elide = 0;
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CPU_FOREACH(cpu) {
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CPUArchState *env = cpu->env_ptr;
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full += atomic_read(&env->tlb_c.full_flush_count);
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part += atomic_read(&env->tlb_c.part_flush_count);
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elide += atomic_read(&env->tlb_c.elide_flush_count);
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}
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*pfull = full;
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*ppart = part;
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*pelide = elide;
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}
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static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
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{
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tlb_table_flush_by_mmuidx(env, mmu_idx);
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memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[0]));
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env->tlb_d[mmu_idx].large_page_addr = -1;
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env->tlb_d[mmu_idx].large_page_mask = -1;
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env->tlb_d[mmu_idx].vindex = 0;
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}
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static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)
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{
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CPUArchState *env = cpu->env_ptr;
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uint16_t asked = data.host_int;
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uint16_t all_dirty, work, to_clean;
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assert_cpu_is_self(cpu);
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tlb_debug("mmu_idx:0x%04" PRIx16 "\n", asked);
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qemu_spin_lock(&env->tlb_c.lock);
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all_dirty = env->tlb_c.dirty;
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to_clean = asked & all_dirty;
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all_dirty &= ~to_clean;
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env->tlb_c.dirty = all_dirty;
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for (work = to_clean; work != 0; work &= work - 1) {
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int mmu_idx = ctz32(work);
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tlb_flush_one_mmuidx_locked(env, mmu_idx);
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}
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qemu_spin_unlock(&env->tlb_c.lock);
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cpu_tb_jmp_cache_clear(cpu);
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if (to_clean == ALL_MMUIDX_BITS) {
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atomic_set(&env->tlb_c.full_flush_count,
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env->tlb_c.full_flush_count + 1);
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} else {
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atomic_set(&env->tlb_c.part_flush_count,
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env->tlb_c.part_flush_count + ctpop16(to_clean));
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if (to_clean != asked) {
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atomic_set(&env->tlb_c.elide_flush_count,
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env->tlb_c.elide_flush_count +
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ctpop16(asked & ~to_clean));
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}
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}
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}
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void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
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{
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tlb_debug("mmu_idx: 0x%" PRIx16 "\n", idxmap);
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if (cpu->created && !qemu_cpu_is_self(cpu)) {
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async_run_on_cpu(cpu, tlb_flush_by_mmuidx_async_work,
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RUN_ON_CPU_HOST_INT(idxmap));
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} else {
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tlb_flush_by_mmuidx_async_work(cpu, RUN_ON_CPU_HOST_INT(idxmap));
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}
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}
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void tlb_flush(CPUState *cpu)
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{
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tlb_flush_by_mmuidx(cpu, ALL_MMUIDX_BITS);
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}
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void tlb_flush_by_mmuidx_all_cpus(CPUState *src_cpu, uint16_t idxmap)
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{
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const run_on_cpu_func fn = tlb_flush_by_mmuidx_async_work;
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tlb_debug("mmu_idx: 0x%"PRIx16"\n", idxmap);
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flush_all_helper(src_cpu, fn, RUN_ON_CPU_HOST_INT(idxmap));
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fn(src_cpu, RUN_ON_CPU_HOST_INT(idxmap));
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}
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void tlb_flush_all_cpus(CPUState *src_cpu)
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{
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tlb_flush_by_mmuidx_all_cpus(src_cpu, ALL_MMUIDX_BITS);
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}
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void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *src_cpu, uint16_t idxmap)
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{
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const run_on_cpu_func fn = tlb_flush_by_mmuidx_async_work;
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tlb_debug("mmu_idx: 0x%"PRIx16"\n", idxmap);
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flush_all_helper(src_cpu, fn, RUN_ON_CPU_HOST_INT(idxmap));
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async_safe_run_on_cpu(src_cpu, fn, RUN_ON_CPU_HOST_INT(idxmap));
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}
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void tlb_flush_all_cpus_synced(CPUState *src_cpu)
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{
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tlb_flush_by_mmuidx_all_cpus_synced(src_cpu, ALL_MMUIDX_BITS);
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}
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static inline bool tlb_hit_page_anyprot(CPUTLBEntry *tlb_entry,
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target_ulong page)
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{
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return tlb_hit_page(tlb_entry->addr_read, page) ||
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tlb_hit_page(tlb_addr_write(tlb_entry), page) ||
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tlb_hit_page(tlb_entry->addr_code, page);
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}
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/**
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* tlb_entry_is_empty - return true if the entry is not in use
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* @te: pointer to CPUTLBEntry
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*/
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static inline bool tlb_entry_is_empty(const CPUTLBEntry *te)
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{
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return te->addr_read == -1 && te->addr_write == -1 && te->addr_code == -1;
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}
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/* Called with tlb_c.lock held */
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static inline bool tlb_flush_entry_locked(CPUTLBEntry *tlb_entry,
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target_ulong page)
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{
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if (tlb_hit_page_anyprot(tlb_entry, page)) {
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memset(tlb_entry, -1, sizeof(*tlb_entry));
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return true;
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}
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return false;
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}
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/* Called with tlb_c.lock held */
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static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_idx,
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target_ulong page)
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{
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int k;
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assert_cpu_is_self(ENV_GET_CPU(env));
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for (k = 0; k < CPU_VTLB_SIZE; k++) {
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if (tlb_flush_entry_locked(&env->tlb_v_table[mmu_idx][k], page)) {
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tlb_n_used_entries_dec(env, mmu_idx);
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}
|
|
}
|
|
}
|
|
|
|
static void tlb_flush_page_locked(CPUArchState *env, int midx,
|
|
target_ulong page)
|
|
{
|
|
target_ulong lp_addr = env->tlb_d[midx].large_page_addr;
|
|
target_ulong lp_mask = env->tlb_d[midx].large_page_mask;
|
|
|
|
/* Check if we need to flush due to large pages. */
|
|
if ((page & lp_mask) == lp_addr) {
|
|
tlb_debug("forcing full flush midx %d ("
|
|
TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
|
|
midx, lp_addr, lp_mask);
|
|
tlb_flush_one_mmuidx_locked(env, midx);
|
|
} else {
|
|
if (tlb_flush_entry_locked(tlb_entry(env, midx, page), page)) {
|
|
tlb_n_used_entries_dec(env, midx);
|
|
}
|
|
tlb_flush_vtlb_page_locked(env, midx, page);
|
|
}
|
|
}
|
|
|
|
/* As we are going to hijack the bottom bits of the page address for a
|
|
* mmuidx bit mask we need to fail to build if we can't do that
|
|
*/
|
|
QEMU_BUILD_BUG_ON(NB_MMU_MODES > TARGET_PAGE_BITS_MIN);
|
|
|
|
static void tlb_flush_page_by_mmuidx_async_work(CPUState *cpu,
|
|
run_on_cpu_data data)
|
|
{
|
|
CPUArchState *env = cpu->env_ptr;
|
|
target_ulong addr_and_mmuidx = (target_ulong) data.target_ptr;
|
|
target_ulong addr = addr_and_mmuidx & TARGET_PAGE_MASK;
|
|
unsigned long mmu_idx_bitmap = addr_and_mmuidx & ALL_MMUIDX_BITS;
|
|
int mmu_idx;
|
|
|
|
assert_cpu_is_self(cpu);
|
|
|
|
tlb_debug("page addr:" TARGET_FMT_lx " mmu_map:0x%lx\n",
|
|
addr, mmu_idx_bitmap);
|
|
|
|
qemu_spin_lock(&env->tlb_c.lock);
|
|
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
|
|
if (test_bit(mmu_idx, &mmu_idx_bitmap)) {
|
|
tlb_flush_page_locked(env, mmu_idx, addr);
|
|
}
|
|
}
|
|
qemu_spin_unlock(&env->tlb_c.lock);
|
|
|
|
tb_flush_jmp_cache(cpu, addr);
|
|
}
|
|
|
|
void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, uint16_t idxmap)
|
|
{
|
|
target_ulong addr_and_mmu_idx;
|
|
|
|
tlb_debug("addr: "TARGET_FMT_lx" mmu_idx:%" PRIx16 "\n", addr, idxmap);
|
|
|
|
/* This should already be page aligned */
|
|
addr_and_mmu_idx = addr & TARGET_PAGE_MASK;
|
|
addr_and_mmu_idx |= idxmap;
|
|
|
|
if (!qemu_cpu_is_self(cpu)) {
|
|
async_run_on_cpu(cpu, tlb_flush_page_by_mmuidx_async_work,
|
|
RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx));
|
|
} else {
|
|
tlb_flush_page_by_mmuidx_async_work(
|
|
cpu, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx));
|
|
}
|
|
}
|
|
|
|
void tlb_flush_page(CPUState *cpu, target_ulong addr)
|
|
{
|
|
tlb_flush_page_by_mmuidx(cpu, addr, ALL_MMUIDX_BITS);
|
|
}
|
|
|
|
void tlb_flush_page_by_mmuidx_all_cpus(CPUState *src_cpu, target_ulong addr,
|
|
uint16_t idxmap)
|
|
{
|
|
const run_on_cpu_func fn = tlb_flush_page_by_mmuidx_async_work;
|
|
target_ulong addr_and_mmu_idx;
|
|
|
|
tlb_debug("addr: "TARGET_FMT_lx" mmu_idx:%"PRIx16"\n", addr, idxmap);
|
|
|
|
/* This should already be page aligned */
|
|
addr_and_mmu_idx = addr & TARGET_PAGE_MASK;
|
|
addr_and_mmu_idx |= idxmap;
|
|
|
|
flush_all_helper(src_cpu, fn, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx));
|
|
fn(src_cpu, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx));
|
|
}
|
|
|
|
void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr)
|
|
{
|
|
tlb_flush_page_by_mmuidx_all_cpus(src, addr, ALL_MMUIDX_BITS);
|
|
}
|
|
|
|
void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
|
|
target_ulong addr,
|
|
uint16_t idxmap)
|
|
{
|
|
const run_on_cpu_func fn = tlb_flush_page_by_mmuidx_async_work;
|
|
target_ulong addr_and_mmu_idx;
|
|
|
|
tlb_debug("addr: "TARGET_FMT_lx" mmu_idx:%"PRIx16"\n", addr, idxmap);
|
|
|
|
/* This should already be page aligned */
|
|
addr_and_mmu_idx = addr & TARGET_PAGE_MASK;
|
|
addr_and_mmu_idx |= idxmap;
|
|
|
|
flush_all_helper(src_cpu, fn, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx));
|
|
async_safe_run_on_cpu(src_cpu, fn, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx));
|
|
}
|
|
|
|
void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr)
|
|
{
|
|
tlb_flush_page_by_mmuidx_all_cpus_synced(src, addr, ALL_MMUIDX_BITS);
|
|
}
|
|
|
|
/* update the TLBs so that writes to code in the virtual page 'addr'
|
|
can be detected */
|
|
void tlb_protect_code(ram_addr_t ram_addr)
|
|
{
|
|
cpu_physical_memory_test_and_clear_dirty(ram_addr, TARGET_PAGE_SIZE,
|
|
DIRTY_MEMORY_CODE);
|
|
}
|
|
|
|
/* update the TLB so that writes in physical page 'phys_addr' are no longer
|
|
tested for self modifying code */
|
|
void tlb_unprotect_code(ram_addr_t ram_addr)
|
|
{
|
|
cpu_physical_memory_set_dirty_flag(ram_addr, DIRTY_MEMORY_CODE);
|
|
}
|
|
|
|
|
|
/*
|
|
* Dirty write flag handling
|
|
*
|
|
* When the TCG code writes to a location it looks up the address in
|
|
* the TLB and uses that data to compute the final address. If any of
|
|
* the lower bits of the address are set then the slow path is forced.
|
|
* There are a number of reasons to do this but for normal RAM the
|
|
* most usual is detecting writes to code regions which may invalidate
|
|
* generated code.
|
|
*
|
|
* Other vCPUs might be reading their TLBs during guest execution, so we update
|
|
* te->addr_write with atomic_set. We don't need to worry about this for
|
|
* oversized guests as MTTCG is disabled for them.
|
|
*
|
|
* Called with tlb_c.lock held.
|
|
*/
|
|
static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry,
|
|
uintptr_t start, uintptr_t length)
|
|
{
|
|
uintptr_t addr = tlb_entry->addr_write;
|
|
|
|
if ((addr & (TLB_INVALID_MASK | TLB_MMIO | TLB_NOTDIRTY)) == 0) {
|
|
addr &= TARGET_PAGE_MASK;
|
|
addr += tlb_entry->addend;
|
|
if ((addr - start) < length) {
|
|
#if TCG_OVERSIZED_GUEST
|
|
tlb_entry->addr_write |= TLB_NOTDIRTY;
|
|
#else
|
|
atomic_set(&tlb_entry->addr_write,
|
|
tlb_entry->addr_write | TLB_NOTDIRTY);
|
|
#endif
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Called with tlb_c.lock held.
|
|
* Called only from the vCPU context, i.e. the TLB's owner thread.
|
|
*/
|
|
static inline void copy_tlb_helper_locked(CPUTLBEntry *d, const CPUTLBEntry *s)
|
|
{
|
|
*d = *s;
|
|
}
|
|
|
|
/* This is a cross vCPU call (i.e. another vCPU resetting the flags of
|
|
* the target vCPU).
|
|
* We must take tlb_c.lock to avoid racing with another vCPU update. The only
|
|
* thing actually updated is the target TLB entry ->addr_write flags.
|
|
*/
|
|
void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length)
|
|
{
|
|
CPUArchState *env;
|
|
|
|
int mmu_idx;
|
|
|
|
env = cpu->env_ptr;
|
|
qemu_spin_lock(&env->tlb_c.lock);
|
|
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
|
|
unsigned int i;
|
|
unsigned int n = tlb_n_entries(env, mmu_idx);
|
|
|
|
for (i = 0; i < n; i++) {
|
|
tlb_reset_dirty_range_locked(&env->tlb_table[mmu_idx][i], start1,
|
|
length);
|
|
}
|
|
|
|
for (i = 0; i < CPU_VTLB_SIZE; i++) {
|
|
tlb_reset_dirty_range_locked(&env->tlb_v_table[mmu_idx][i], start1,
|
|
length);
|
|
}
|
|
}
|
|
qemu_spin_unlock(&env->tlb_c.lock);
|
|
}
|
|
|
|
/* Called with tlb_c.lock held */
|
|
static inline void tlb_set_dirty1_locked(CPUTLBEntry *tlb_entry,
|
|
target_ulong vaddr)
|
|
{
|
|
if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) {
|
|
tlb_entry->addr_write = vaddr;
|
|
}
|
|
}
|
|
|
|
/* update the TLB corresponding to virtual page vaddr
|
|
so that it is no longer dirty */
|
|
void tlb_set_dirty(CPUState *cpu, target_ulong vaddr)
|
|
{
|
|
CPUArchState *env = cpu->env_ptr;
|
|
int mmu_idx;
|
|
|
|
assert_cpu_is_self(cpu);
|
|
|
|
vaddr &= TARGET_PAGE_MASK;
|
|
qemu_spin_lock(&env->tlb_c.lock);
|
|
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
|
|
tlb_set_dirty1_locked(tlb_entry(env, mmu_idx, vaddr), vaddr);
|
|
}
|
|
|
|
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
|
|
int k;
|
|
for (k = 0; k < CPU_VTLB_SIZE; k++) {
|
|
tlb_set_dirty1_locked(&env->tlb_v_table[mmu_idx][k], vaddr);
|
|
}
|
|
}
|
|
qemu_spin_unlock(&env->tlb_c.lock);
|
|
}
|
|
|
|
/* Our TLB does not support large pages, so remember the area covered by
|
|
large pages and trigger a full TLB flush if these are invalidated. */
|
|
static void tlb_add_large_page(CPUArchState *env, int mmu_idx,
|
|
target_ulong vaddr, target_ulong size)
|
|
{
|
|
target_ulong lp_addr = env->tlb_d[mmu_idx].large_page_addr;
|
|
target_ulong lp_mask = ~(size - 1);
|
|
|
|
if (lp_addr == (target_ulong)-1) {
|
|
/* No previous large page. */
|
|
lp_addr = vaddr;
|
|
} else {
|
|
/* Extend the existing region to include the new page.
|
|
This is a compromise between unnecessary flushes and
|
|
the cost of maintaining a full variable size TLB. */
|
|
lp_mask &= env->tlb_d[mmu_idx].large_page_mask;
|
|
while (((lp_addr ^ vaddr) & lp_mask) != 0) {
|
|
lp_mask <<= 1;
|
|
}
|
|
}
|
|
env->tlb_d[mmu_idx].large_page_addr = lp_addr & lp_mask;
|
|
env->tlb_d[mmu_idx].large_page_mask = lp_mask;
|
|
}
|
|
|
|
/* Add a new TLB entry. At most one entry for a given virtual address
|
|
* is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
|
|
* supplied size is only used by tlb_flush_page.
|
|
*
|
|
* Called from TCG-generated code, which is under an RCU read-side
|
|
* critical section.
|
|
*/
|
|
void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
|
|
hwaddr paddr, MemTxAttrs attrs, int prot,
|
|
int mmu_idx, target_ulong size)
|
|
{
|
|
CPUArchState *env = cpu->env_ptr;
|
|
MemoryRegionSection *section;
|
|
unsigned int index;
|
|
target_ulong address;
|
|
target_ulong code_address;
|
|
uintptr_t addend;
|
|
CPUTLBEntry *te, tn;
|
|
hwaddr iotlb, xlat, sz, paddr_page;
|
|
target_ulong vaddr_page;
|
|
int asidx = cpu_asidx_from_attrs(cpu, attrs);
|
|
|
|
assert_cpu_is_self(cpu);
|
|
|
|
if (size <= TARGET_PAGE_SIZE) {
|
|
sz = TARGET_PAGE_SIZE;
|
|
} else {
|
|
tlb_add_large_page(env, mmu_idx, vaddr, size);
|
|
sz = size;
|
|
}
|
|
vaddr_page = vaddr & TARGET_PAGE_MASK;
|
|
paddr_page = paddr & TARGET_PAGE_MASK;
|
|
|
|
section = address_space_translate_for_iotlb(cpu, asidx, paddr_page,
|
|
&xlat, &sz, attrs, &prot);
|
|
assert(sz >= TARGET_PAGE_SIZE);
|
|
|
|
tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
|
|
" prot=%x idx=%d\n",
|
|
vaddr, paddr, prot, mmu_idx);
|
|
|
|
address = vaddr_page;
|
|
if (size < TARGET_PAGE_SIZE) {
|
|
/*
|
|
* Slow-path the TLB entries; we will repeat the MMU check and TLB
|
|
* fill on every access.
|
|
*/
|
|
address |= TLB_RECHECK;
|
|
}
|
|
if (!memory_region_is_ram(section->mr) &&
|
|
!memory_region_is_romd(section->mr)) {
|
|
/* IO memory case */
|
|
address |= TLB_MMIO;
|
|
addend = 0;
|
|
} else {
|
|
/* TLB_MMIO for rom/romd handled below */
|
|
addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat;
|
|
}
|
|
|
|
code_address = address;
|
|
iotlb = memory_region_section_get_iotlb(cpu, section, vaddr_page,
|
|
paddr_page, xlat, prot, &address);
|
|
|
|
index = tlb_index(env, mmu_idx, vaddr_page);
|
|
te = tlb_entry(env, mmu_idx, vaddr_page);
|
|
|
|
/*
|
|
* Hold the TLB lock for the rest of the function. We could acquire/release
|
|
* the lock several times in the function, but it is faster to amortize the
|
|
* acquisition cost by acquiring it just once. Note that this leads to
|
|
* a longer critical section, but this is not a concern since the TLB lock
|
|
* is unlikely to be contended.
|
|
*/
|
|
qemu_spin_lock(&env->tlb_c.lock);
|
|
|
|
/* Note that the tlb is no longer clean. */
|
|
env->tlb_c.dirty |= 1 << mmu_idx;
|
|
|
|
/* Make sure there's no cached translation for the new page. */
|
|
tlb_flush_vtlb_page_locked(env, mmu_idx, vaddr_page);
|
|
|
|
/*
|
|
* Only evict the old entry to the victim tlb if it's for a
|
|
* different page; otherwise just overwrite the stale data.
|
|
*/
|
|
if (!tlb_hit_page_anyprot(te, vaddr_page) && !tlb_entry_is_empty(te)) {
|
|
unsigned vidx = env->tlb_d[mmu_idx].vindex++ % CPU_VTLB_SIZE;
|
|
CPUTLBEntry *tv = &env->tlb_v_table[mmu_idx][vidx];
|
|
|
|
/* Evict the old entry into the victim tlb. */
|
|
copy_tlb_helper_locked(tv, te);
|
|
env->iotlb_v[mmu_idx][vidx] = env->iotlb[mmu_idx][index];
|
|
tlb_n_used_entries_dec(env, mmu_idx);
|
|
}
|
|
|
|
/* refill the tlb */
|
|
/*
|
|
* At this point iotlb contains a physical section number in the lower
|
|
* TARGET_PAGE_BITS, and either
|
|
* + the ram_addr_t of the page base of the target RAM (if NOTDIRTY or ROM)
|
|
* + the offset within section->mr of the page base (otherwise)
|
|
* We subtract the vaddr_page (which is page aligned and thus won't
|
|
* disturb the low bits) to give an offset which can be added to the
|
|
* (non-page-aligned) vaddr of the eventual memory access to get
|
|
* the MemoryRegion offset for the access. Note that the vaddr we
|
|
* subtract here is that of the page base, and not the same as the
|
|
* vaddr we add back in io_readx()/io_writex()/get_page_addr_code().
|
|
*/
|
|
env->iotlb[mmu_idx][index].addr = iotlb - vaddr_page;
|
|
env->iotlb[mmu_idx][index].attrs = attrs;
|
|
|
|
/* Now calculate the new entry */
|
|
tn.addend = addend - vaddr_page;
|
|
if (prot & PAGE_READ) {
|
|
tn.addr_read = address;
|
|
} else {
|
|
tn.addr_read = -1;
|
|
}
|
|
|
|
if (prot & PAGE_EXEC) {
|
|
tn.addr_code = code_address;
|
|
} else {
|
|
tn.addr_code = -1;
|
|
}
|
|
|
|
tn.addr_write = -1;
|
|
if (prot & PAGE_WRITE) {
|
|
if ((memory_region_is_ram(section->mr) && section->readonly)
|
|
|| memory_region_is_romd(section->mr)) {
|
|
/* Write access calls the I/O callback. */
|
|
tn.addr_write = address | TLB_MMIO;
|
|
} else if (memory_region_is_ram(section->mr)
|
|
&& cpu_physical_memory_is_clean(
|
|
memory_region_get_ram_addr(section->mr) + xlat)) {
|
|
tn.addr_write = address | TLB_NOTDIRTY;
|
|
} else {
|
|
tn.addr_write = address;
|
|
}
|
|
if (prot & PAGE_WRITE_INV) {
|
|
tn.addr_write |= TLB_INVALID_MASK;
|
|
}
|
|
}
|
|
|
|
copy_tlb_helper_locked(te, &tn);
|
|
tlb_n_used_entries_inc(env, mmu_idx);
|
|
qemu_spin_unlock(&env->tlb_c.lock);
|
|
}
|
|
|
|
/* Add a new TLB entry, but without specifying the memory
|
|
* transaction attributes to be used.
|
|
*/
|
|
void tlb_set_page(CPUState *cpu, target_ulong vaddr,
|
|
hwaddr paddr, int prot,
|
|
int mmu_idx, target_ulong size)
|
|
{
|
|
tlb_set_page_with_attrs(cpu, vaddr, paddr, MEMTXATTRS_UNSPECIFIED,
|
|
prot, mmu_idx, size);
|
|
}
|
|
|
|
static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
|
|
{
|
|
ram_addr_t ram_addr;
|
|
|
|
ram_addr = qemu_ram_addr_from_host(ptr);
|
|
if (ram_addr == RAM_ADDR_INVALID) {
|
|
error_report("Bad ram pointer %p", ptr);
|
|
abort();
|
|
}
|
|
return ram_addr;
|
|
}
|
|
|
|
static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
|
|
int mmu_idx,
|
|
target_ulong addr, uintptr_t retaddr,
|
|
bool recheck, MMUAccessType access_type, int size)
|
|
{
|
|
CPUState *cpu = ENV_GET_CPU(env);
|
|
hwaddr mr_offset;
|
|
MemoryRegionSection *section;
|
|
MemoryRegion *mr;
|
|
uint64_t val;
|
|
bool locked = false;
|
|
MemTxResult r;
|
|
|
|
if (recheck) {
|
|
/*
|
|
* This is a TLB_RECHECK access, where the MMU protection
|
|
* covers a smaller range than a target page, and we must
|
|
* repeat the MMU check here. This tlb_fill() call might
|
|
* longjump out if this access should cause a guest exception.
|
|
*/
|
|
CPUTLBEntry *entry;
|
|
target_ulong tlb_addr;
|
|
|
|
tlb_fill(cpu, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
|
|
|
|
entry = tlb_entry(env, mmu_idx, addr);
|
|
tlb_addr = entry->addr_read;
|
|
if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) {
|
|
/* RAM access */
|
|
uintptr_t haddr = addr + entry->addend;
|
|
|
|
return ldn_p((void *)haddr, size);
|
|
}
|
|
/* Fall through for handling IO accesses */
|
|
}
|
|
|
|
section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
|
|
mr = section->mr;
|
|
mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
|
|
cpu->mem_io_pc = retaddr;
|
|
if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu->can_do_io) {
|
|
cpu_io_recompile(cpu, retaddr);
|
|
}
|
|
|
|
cpu->mem_io_vaddr = addr;
|
|
cpu->mem_io_access_type = access_type;
|
|
|
|
if (mr->global_locking && !qemu_mutex_iothread_locked()) {
|
|
qemu_mutex_lock_iothread();
|
|
locked = true;
|
|
}
|
|
r = memory_region_dispatch_read(mr, mr_offset,
|
|
&val, size, iotlbentry->attrs);
|
|
if (r != MEMTX_OK) {
|
|
hwaddr physaddr = mr_offset +
|
|
section->offset_within_address_space -
|
|
section->offset_within_region;
|
|
|
|
cpu_transaction_failed(cpu, physaddr, addr, size, access_type,
|
|
mmu_idx, iotlbentry->attrs, r, retaddr);
|
|
}
|
|
if (locked) {
|
|
qemu_mutex_unlock_iothread();
|
|
}
|
|
|
|
return val;
|
|
}
|
|
|
|
static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
|
|
int mmu_idx,
|
|
uint64_t val, target_ulong addr,
|
|
uintptr_t retaddr, bool recheck, int size)
|
|
{
|
|
CPUState *cpu = ENV_GET_CPU(env);
|
|
hwaddr mr_offset;
|
|
MemoryRegionSection *section;
|
|
MemoryRegion *mr;
|
|
bool locked = false;
|
|
MemTxResult r;
|
|
|
|
if (recheck) {
|
|
/*
|
|
* This is a TLB_RECHECK access, where the MMU protection
|
|
* covers a smaller range than a target page, and we must
|
|
* repeat the MMU check here. This tlb_fill() call might
|
|
* longjump out if this access should cause a guest exception.
|
|
*/
|
|
CPUTLBEntry *entry;
|
|
target_ulong tlb_addr;
|
|
|
|
tlb_fill(cpu, addr, size, MMU_DATA_STORE, mmu_idx, retaddr);
|
|
|
|
entry = tlb_entry(env, mmu_idx, addr);
|
|
tlb_addr = tlb_addr_write(entry);
|
|
if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) {
|
|
/* RAM access */
|
|
uintptr_t haddr = addr + entry->addend;
|
|
|
|
stn_p((void *)haddr, size, val);
|
|
return;
|
|
}
|
|
/* Fall through for handling IO accesses */
|
|
}
|
|
|
|
section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
|
|
mr = section->mr;
|
|
mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
|
|
if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu->can_do_io) {
|
|
cpu_io_recompile(cpu, retaddr);
|
|
}
|
|
cpu->mem_io_vaddr = addr;
|
|
cpu->mem_io_pc = retaddr;
|
|
|
|
if (mr->global_locking && !qemu_mutex_iothread_locked()) {
|
|
qemu_mutex_lock_iothread();
|
|
locked = true;
|
|
}
|
|
r = memory_region_dispatch_write(mr, mr_offset,
|
|
val, size, iotlbentry->attrs);
|
|
if (r != MEMTX_OK) {
|
|
hwaddr physaddr = mr_offset +
|
|
section->offset_within_address_space -
|
|
section->offset_within_region;
|
|
|
|
cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_STORE,
|
|
mmu_idx, iotlbentry->attrs, r, retaddr);
|
|
}
|
|
if (locked) {
|
|
qemu_mutex_unlock_iothread();
|
|
}
|
|
}
|
|
|
|
/* Return true if ADDR is present in the victim tlb, and has been copied
|
|
back to the main tlb. */
|
|
static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index,
|
|
size_t elt_ofs, target_ulong page)
|
|
{
|
|
size_t vidx;
|
|
|
|
assert_cpu_is_self(ENV_GET_CPU(env));
|
|
for (vidx = 0; vidx < CPU_VTLB_SIZE; ++vidx) {
|
|
CPUTLBEntry *vtlb = &env->tlb_v_table[mmu_idx][vidx];
|
|
target_ulong cmp;
|
|
|
|
/* elt_ofs might correspond to .addr_write, so use atomic_read */
|
|
#if TCG_OVERSIZED_GUEST
|
|
cmp = *(target_ulong *)((uintptr_t)vtlb + elt_ofs);
|
|
#else
|
|
cmp = atomic_read((target_ulong *)((uintptr_t)vtlb + elt_ofs));
|
|
#endif
|
|
|
|
if (cmp == page) {
|
|
/* Found entry in victim tlb, swap tlb and iotlb. */
|
|
CPUTLBEntry tmptlb, *tlb = &env->tlb_table[mmu_idx][index];
|
|
|
|
qemu_spin_lock(&env->tlb_c.lock);
|
|
copy_tlb_helper_locked(&tmptlb, tlb);
|
|
copy_tlb_helper_locked(tlb, vtlb);
|
|
copy_tlb_helper_locked(vtlb, &tmptlb);
|
|
qemu_spin_unlock(&env->tlb_c.lock);
|
|
|
|
CPUIOTLBEntry tmpio, *io = &env->iotlb[mmu_idx][index];
|
|
CPUIOTLBEntry *vio = &env->iotlb_v[mmu_idx][vidx];
|
|
tmpio = *io; *io = *vio; *vio = tmpio;
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/* Macro to call the above, with local variables from the use context. */
|
|
#define VICTIM_TLB_HIT(TY, ADDR) \
|
|
victim_tlb_hit(env, mmu_idx, index, offsetof(CPUTLBEntry, TY), \
|
|
(ADDR) & TARGET_PAGE_MASK)
|
|
|
|
/* NOTE: this function can trigger an exception */
|
|
/* NOTE2: the returned address is not exactly the physical address: it
|
|
* is actually a ram_addr_t (in system mode; the user mode emulation
|
|
* version of this function returns a guest virtual address).
|
|
*/
|
|
tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr)
|
|
{
|
|
uintptr_t mmu_idx = cpu_mmu_index(env, true);
|
|
uintptr_t index = tlb_index(env, mmu_idx, addr);
|
|
CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
|
|
void *p;
|
|
|
|
if (unlikely(!tlb_hit(entry->addr_code, addr))) {
|
|
if (!VICTIM_TLB_HIT(addr_code, addr)) {
|
|
tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0);
|
|
}
|
|
assert(tlb_hit(entry->addr_code, addr));
|
|
}
|
|
|
|
if (unlikely(entry->addr_code & (TLB_RECHECK | TLB_MMIO))) {
|
|
/*
|
|
* Return -1 if we can't translate and execute from an entire
|
|
* page of RAM here, which will cause us to execute by loading
|
|
* and translating one insn at a time, without caching:
|
|
* - TLB_RECHECK: means the MMU protection covers a smaller range
|
|
* than a target page, so we must redo the MMU check every insn
|
|
* - TLB_MMIO: region is not backed by RAM
|
|
*/
|
|
return -1;
|
|
}
|
|
|
|
p = (void *)((uintptr_t)addr + entry->addend);
|
|
return qemu_ram_addr_from_host_nofail(p);
|
|
}
|
|
|
|
/* Probe for whether the specified guest write access is permitted.
|
|
* If it is not permitted then an exception will be taken in the same
|
|
* way as if this were a real write access (and we will not return).
|
|
* Otherwise the function will return, and there will be a valid
|
|
* entry in the TLB for this access.
|
|
*/
|
|
void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
|
|
uintptr_t retaddr)
|
|
{
|
|
uintptr_t index = tlb_index(env, mmu_idx, addr);
|
|
CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
|
|
|
|
if (!tlb_hit(tlb_addr_write(entry), addr)) {
|
|
/* TLB entry is for a different page */
|
|
if (!VICTIM_TLB_HIT(addr_write, addr)) {
|
|
tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE,
|
|
mmu_idx, retaddr);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Probe for a read-modify-write atomic operation. Do not allow unaligned
|
|
* operations, or io operations to proceed. Return the host address. */
|
|
static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
|
|
TCGMemOpIdx oi, uintptr_t retaddr,
|
|
NotDirtyInfo *ndi)
|
|
{
|
|
size_t mmu_idx = get_mmuidx(oi);
|
|
uintptr_t index = tlb_index(env, mmu_idx, addr);
|
|
CPUTLBEntry *tlbe = tlb_entry(env, mmu_idx, addr);
|
|
target_ulong tlb_addr = tlb_addr_write(tlbe);
|
|
TCGMemOp mop = get_memop(oi);
|
|
int a_bits = get_alignment_bits(mop);
|
|
int s_bits = mop & MO_SIZE;
|
|
void *hostaddr;
|
|
|
|
/* Adjust the given return address. */
|
|
retaddr -= GETPC_ADJ;
|
|
|
|
/* Enforce guest required alignment. */
|
|
if (unlikely(a_bits > 0 && (addr & ((1 << a_bits) - 1)))) {
|
|
/* ??? Maybe indicate atomic op to cpu_unaligned_access */
|
|
cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
|
|
mmu_idx, retaddr);
|
|
}
|
|
|
|
/* Enforce qemu required alignment. */
|
|
if (unlikely(addr & ((1 << s_bits) - 1))) {
|
|
/* We get here if guest alignment was not requested,
|
|
or was not enforced by cpu_unaligned_access above.
|
|
We might widen the access and emulate, but for now
|
|
mark an exception and exit the cpu loop. */
|
|
goto stop_the_world;
|
|
}
|
|
|
|
/* Check TLB entry and enforce page permissions. */
|
|
if (!tlb_hit(tlb_addr, addr)) {
|
|
if (!VICTIM_TLB_HIT(addr_write, addr)) {
|
|
tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_STORE,
|
|
mmu_idx, retaddr);
|
|
}
|
|
tlb_addr = tlb_addr_write(tlbe) & ~TLB_INVALID_MASK;
|
|
}
|
|
|
|
/* Notice an IO access or a needs-MMU-lookup access */
|
|
if (unlikely(tlb_addr & (TLB_MMIO | TLB_RECHECK))) {
|
|
/* There's really nothing that can be done to
|
|
support this apart from stop-the-world. */
|
|
goto stop_the_world;
|
|
}
|
|
|
|
/* Let the guest notice RMW on a write-only page. */
|
|
if (unlikely(tlbe->addr_read != (tlb_addr & ~TLB_NOTDIRTY))) {
|
|
tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_LOAD,
|
|
mmu_idx, retaddr);
|
|
/* Since we don't support reads and writes to different addresses,
|
|
and we do have the proper page loaded for write, this shouldn't
|
|
ever return. But just in case, handle via stop-the-world. */
|
|
goto stop_the_world;
|
|
}
|
|
|
|
hostaddr = (void *)((uintptr_t)addr + tlbe->addend);
|
|
|
|
ndi->active = false;
|
|
if (unlikely(tlb_addr & TLB_NOTDIRTY)) {
|
|
ndi->active = true;
|
|
memory_notdirty_write_prepare(ndi, ENV_GET_CPU(env), addr,
|
|
qemu_ram_addr_from_host_nofail(hostaddr),
|
|
1 << s_bits);
|
|
}
|
|
|
|
return hostaddr;
|
|
|
|
stop_the_world:
|
|
cpu_loop_exit_atomic(ENV_GET_CPU(env), retaddr);
|
|
}
|
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
# define TGT_BE(X) (X)
|
|
# define TGT_LE(X) BSWAP(X)
|
|
#else
|
|
# define TGT_BE(X) BSWAP(X)
|
|
# define TGT_LE(X) (X)
|
|
#endif
|
|
|
|
#define MMUSUFFIX _mmu
|
|
|
|
#define DATA_SIZE 1
|
|
#include "softmmu_template.h"
|
|
|
|
#define DATA_SIZE 2
|
|
#include "softmmu_template.h"
|
|
|
|
#define DATA_SIZE 4
|
|
#include "softmmu_template.h"
|
|
|
|
#define DATA_SIZE 8
|
|
#include "softmmu_template.h"
|
|
|
|
/* First set of helpers allows passing in of OI and RETADDR. This makes
|
|
them callable from other helpers. */
|
|
|
|
#define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr
|
|
#define ATOMIC_NAME(X) \
|
|
HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu))
|
|
#define ATOMIC_MMU_DECLS NotDirtyInfo ndi
|
|
#define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, oi, retaddr, &ndi)
|
|
#define ATOMIC_MMU_CLEANUP \
|
|
do { \
|
|
if (unlikely(ndi.active)) { \
|
|
memory_notdirty_write_complete(&ndi); \
|
|
} \
|
|
} while (0)
|
|
|
|
#define DATA_SIZE 1
|
|
#include "atomic_template.h"
|
|
|
|
#define DATA_SIZE 2
|
|
#include "atomic_template.h"
|
|
|
|
#define DATA_SIZE 4
|
|
#include "atomic_template.h"
|
|
|
|
#ifdef CONFIG_ATOMIC64
|
|
#define DATA_SIZE 8
|
|
#include "atomic_template.h"
|
|
#endif
|
|
|
|
#if HAVE_CMPXCHG128 || HAVE_ATOMIC128
|
|
#define DATA_SIZE 16
|
|
#include "atomic_template.h"
|
|
#endif
|
|
|
|
/* Second set of helpers are directly callable from TCG as helpers. */
|
|
|
|
#undef EXTRA_ARGS
|
|
#undef ATOMIC_NAME
|
|
#undef ATOMIC_MMU_LOOKUP
|
|
#define EXTRA_ARGS , TCGMemOpIdx oi
|
|
#define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END))
|
|
#define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, oi, GETPC(), &ndi)
|
|
|
|
#define DATA_SIZE 1
|
|
#include "atomic_template.h"
|
|
|
|
#define DATA_SIZE 2
|
|
#include "atomic_template.h"
|
|
|
|
#define DATA_SIZE 4
|
|
#include "atomic_template.h"
|
|
|
|
#ifdef CONFIG_ATOMIC64
|
|
#define DATA_SIZE 8
|
|
#include "atomic_template.h"
|
|
#endif
|
|
|
|
/* Code access functions. */
|
|
|
|
#undef MMUSUFFIX
|
|
#define MMUSUFFIX _cmmu
|
|
#undef GETPC
|
|
#define GETPC() ((uintptr_t)0)
|
|
#define SOFTMMU_CODE_ACCESS
|
|
|
|
#define DATA_SIZE 1
|
|
#include "softmmu_template.h"
|
|
|
|
#define DATA_SIZE 2
|
|
#include "softmmu_template.h"
|
|
|
|
#define DATA_SIZE 4
|
|
#include "softmmu_template.h"
|
|
|
|
#define DATA_SIZE 8
|
|
#include "softmmu_template.h"
|