qemu-patch-raspberry4/target/riscv/insn_trans
Philipp Tomsich 45d1749c1c target/riscv: clwz must ignore high bits (use shift-left & changed logic)
Assume clzw being executed on a register that is not sign-extended, such
as for the following sequence that uses (1ULL << 63) | 392 as the operand
to clzw:
	bseti	a2, zero, 63
	addi	a2, a2, 392
	clzw    a3, a2
The correct result of clzw would be 23, but the current implementation
returns -32 (as it performs a 64bit clz, which results in 0 leading zero
bits, and then subtracts 32).

Fix this by changing the implementation to:
 1. shift the original register up by 32
 2. performs a target-length (64bit) clz
 3. return 32 if no bits are set

Marking this instruction as 'w-form' (i.e., setting ctx->w) would not
correctly model the behaviour, as the instruction should not perform
a zero-extensions on the input (after all, it is not a .uw instruction)
and the result is always in the range 0..32 (so neither a sign-extension
nor a zero-extension on the result will ever be needed).  Consequently,
we do not set ctx->w and mark the instruction as EXT_NONE.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
Message-id: 20210911140016.834071-4-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-07 08:32:47 +10:00
..
trans_privileged.c.inc riscv: Add semihosting support 2021-01-18 10:05:06 +00:00
trans_rva.c.inc target/riscv: Use {get,dest}_gpr for RVA 2021-09-01 11:59:12 +10:00
trans_rvb.c.inc target/riscv: clwz must ignore high bits (use shift-left & changed logic) 2021-10-07 08:32:47 +10:00
trans_rvd.c.inc target/riscv: Use {get,dest}_gpr for RVD 2021-09-01 11:59:12 +10:00
trans_rvf.c.inc target/riscv: Use {get,dest}_gpr for RVF 2021-09-01 11:59:12 +10:00
trans_rvh.c.inc target/riscv: Tidy trans_rvh.c.inc 2021-09-01 11:59:12 +10:00
trans_rvi.c.inc target/riscv: Reorg csr instructions 2021-09-01 11:59:12 +10:00
trans_rvm.c.inc target/riscv: Move gen_* helpers for RVM 2021-09-01 11:59:12 +10:00
trans_rvv.c.inc target/riscv: Use {get,dest}_gpr for RVV 2021-09-01 11:59:12 +10:00