qemu-patch-raspberry4/include/hw/riscv
Bin Meng 898dc008e8 hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card
Microchip PolarFire SoC integrates one Cadence SDHCI controller.
On the Icicle Kit board, one eMMC chip and an external SD card
connect to this controller depending on different configuration.

As QEMU does not support eMMC yet, we just emulate the SD card
configuration. To test this, the Hart Software Services (HSS)
should choose the SD card configuration:

$ cp boards/icicle-kit-es/def_config.sdcard .config
$ make BOARD=icicle-kit-es

The SD card image can be built from the Yocto BSP at:
https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp

Note the generated SD card image should be resized before use:
$ qemu-img resize /path/to/sdcard.img 4G

Launch QEMU with the following command:
$ qemu-system-riscv64 -nographic -M microchip-icicle-kit -sd sdcard.img

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09 15:54:18 -07:00
..
boot.h riscv: Add opensbi firmware dynamic support 2020-07-13 17:25:37 -07:00
boot_opensbi.h riscv: Add opensbi firmware dynamic support 2020-07-13 17:25:37 -07:00
microchip_pfsoc.h hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card 2020-09-09 15:54:18 -07:00
numa.h hw/riscv: Add helpers for RISC-V multi-socket NUMA machines 2020-08-25 09:11:35 -07:00
opentitan.h opentitan: Rename memmap enum constants 2020-08-27 14:04:54 -04:00
riscv_hart.h hw/riscv: hart: Add a new 'resetvec' property 2020-09-09 15:54:18 -07:00
riscv_htif.h Clean up inclusion of sysemu/sysemu.h 2019-08-16 13:31:53 +02:00
sifive_clint.h hw/riscv: Allow creating multiple instances of CLINT 2020-08-25 09:11:35 -07:00
sifive_cpu.h riscv: Add a sifive_cpu.h to include both E and U cpu type defines 2019-09-17 08:42:46 -07:00
sifive_e.h sifive_e: Support the revB machine 2020-06-19 08:24:07 -07:00
sifive_e_prci.h riscv: sifive_e: prci: Update the PRCI register block size 2019-09-17 08:42:46 -07:00
sifive_gpio.h hw/riscv: sifive_gpio: Add a new 'ngpio' property 2020-06-19 08:24:07 -07:00
sifive_plic.h hw/riscv: Allow creating multiple instances of PLIC 2020-08-25 09:11:35 -07:00
sifive_test.h riscv: sifive_test: Add reset functionality 2019-09-17 08:42:44 -07:00
sifive_u.h hw/riscv: sifive_u: Add a dummy L2 cache controller device 2020-08-21 22:37:55 -07:00
sifive_u_otp.h riscv: sifive: Implement a model for SiFive FU540 OTP 2019-09-17 08:42:49 -07:00
sifive_u_prci.h riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes 2019-09-17 08:42:48 -07:00
sifive_uart.h include: Make headers more self-contained 2019-08-16 13:31:51 +02:00
spike.h hw/riscv: spike: Allow creating multiple NUMA sockets 2020-08-25 09:11:35 -07:00
virt.h hw/riscv: virt: Allow creating multiple NUMA sockets 2020-08-25 09:11:35 -07:00