This is needed to dynamically add SLIC tables with Windows activation keys. Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6650 c046a42c-6fe2-441c-8c8c-71466251a162
918 lines
22 KiB
C
918 lines
22 KiB
C
/*
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* ACPI implementation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
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*/
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#include "hw.h"
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#include "pc.h"
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#include "pci.h"
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#include "qemu-timer.h"
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#include "sysemu.h"
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#include "i2c.h"
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#include "smbus.h"
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#include "kvm.h"
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//#define DEBUG
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/* i82731AB (PIIX4) compatible power management function */
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#define PM_FREQ 3579545
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#define ACPI_DBG_IO_ADDR 0xb044
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typedef struct PIIX4PMState {
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PCIDevice dev;
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uint16_t pmsts;
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uint16_t pmen;
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uint16_t pmcntrl;
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uint8_t apmc;
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uint8_t apms;
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QEMUTimer *tmr_timer;
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int64_t tmr_overflow_time;
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i2c_bus *smbus;
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uint8_t smb_stat;
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uint8_t smb_ctl;
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uint8_t smb_cmd;
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uint8_t smb_addr;
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uint8_t smb_data0;
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uint8_t smb_data1;
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uint8_t smb_data[32];
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uint8_t smb_index;
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qemu_irq irq;
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} PIIX4PMState;
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#define RSM_STS (1 << 15)
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#define PWRBTN_STS (1 << 8)
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#define RTC_EN (1 << 10)
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#define PWRBTN_EN (1 << 8)
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#define GBL_EN (1 << 5)
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#define TMROF_EN (1 << 0)
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#define SCI_EN (1 << 0)
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#define SUS_EN (1 << 13)
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#define ACPI_ENABLE 0xf1
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#define ACPI_DISABLE 0xf0
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#define SMBHSTSTS 0x00
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#define SMBHSTCNT 0x02
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#define SMBHSTCMD 0x03
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#define SMBHSTADD 0x04
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#define SMBHSTDAT0 0x05
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#define SMBHSTDAT1 0x06
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#define SMBBLKDAT 0x07
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static PIIX4PMState *pm_state;
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static uint32_t get_pmtmr(PIIX4PMState *s)
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{
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uint32_t d;
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d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
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return d & 0xffffff;
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}
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static int get_pmsts(PIIX4PMState *s)
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{
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int64_t d;
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int pmsts;
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pmsts = s->pmsts;
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d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
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if (d >= s->tmr_overflow_time)
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s->pmsts |= TMROF_EN;
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return s->pmsts;
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}
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static void pm_update_sci(PIIX4PMState *s)
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{
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int sci_level, pmsts;
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int64_t expire_time;
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pmsts = get_pmsts(s);
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sci_level = (((pmsts & s->pmen) &
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(RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
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qemu_set_irq(s->irq, sci_level);
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/* schedule a timer interruption if needed */
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if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
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expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
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qemu_mod_timer(s->tmr_timer, expire_time);
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} else {
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qemu_del_timer(s->tmr_timer);
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}
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}
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static void pm_tmr_timer(void *opaque)
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{
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PIIX4PMState *s = opaque;
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pm_update_sci(s);
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}
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static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
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{
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PIIX4PMState *s = opaque;
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addr &= 0x3f;
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switch(addr) {
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case 0x00:
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{
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int64_t d;
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int pmsts;
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pmsts = get_pmsts(s);
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if (pmsts & val & TMROF_EN) {
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/* if TMRSTS is reset, then compute the new overflow time */
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d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
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s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
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}
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s->pmsts &= ~val;
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pm_update_sci(s);
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}
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break;
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case 0x02:
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s->pmen = val;
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pm_update_sci(s);
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break;
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case 0x04:
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{
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int sus_typ;
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s->pmcntrl = val & ~(SUS_EN);
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if (val & SUS_EN) {
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/* change suspend type */
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sus_typ = (val >> 10) & 7;
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switch(sus_typ) {
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case 0: /* soft power off */
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qemu_system_shutdown_request();
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break;
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case 1:
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/* RSM_STS should be set on resume. Pretend that resume
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was caused by power button */
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s->pmsts |= (RSM_STS | PWRBTN_STS);
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qemu_system_reset_request();
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#if defined(TARGET_I386)
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cmos_set_s3_resume();
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#endif
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default:
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break;
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}
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}
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}
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break;
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default:
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break;
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}
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#ifdef DEBUG
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printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
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#endif
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}
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static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
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{
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PIIX4PMState *s = opaque;
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uint32_t val;
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addr &= 0x3f;
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switch(addr) {
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case 0x00:
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val = get_pmsts(s);
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break;
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case 0x02:
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val = s->pmen;
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break;
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case 0x04:
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val = s->pmcntrl;
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break;
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default:
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val = 0;
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break;
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}
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#ifdef DEBUG
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printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
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#endif
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return val;
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}
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static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
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{
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// PIIX4PMState *s = opaque;
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addr &= 0x3f;
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#ifdef DEBUG
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printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
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#endif
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}
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static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
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{
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PIIX4PMState *s = opaque;
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uint32_t val;
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addr &= 0x3f;
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switch(addr) {
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case 0x08:
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val = get_pmtmr(s);
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break;
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default:
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val = 0;
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break;
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}
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#ifdef DEBUG
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printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
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#endif
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return val;
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}
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static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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PIIX4PMState *s = opaque;
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addr &= 1;
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#ifdef DEBUG
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printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
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#endif
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if (addr == 0) {
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s->apmc = val;
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/* ACPI specs 3.0, 4.7.2.5 */
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if (val == ACPI_ENABLE) {
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s->pmcntrl |= SCI_EN;
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} else if (val == ACPI_DISABLE) {
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s->pmcntrl &= ~SCI_EN;
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}
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if (s->dev.config[0x5b] & (1 << 1)) {
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cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
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}
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} else {
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s->apms = val;
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}
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}
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static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
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{
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PIIX4PMState *s = opaque;
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uint32_t val;
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addr &= 1;
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if (addr == 0) {
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val = s->apmc;
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} else {
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val = s->apms;
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}
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#ifdef DEBUG
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printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
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#endif
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return val;
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}
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static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
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{
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#if defined(DEBUG)
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printf("ACPI: DBG: 0x%08x\n", val);
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#endif
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}
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static void smb_transaction(PIIX4PMState *s)
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{
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uint8_t prot = (s->smb_ctl >> 2) & 0x07;
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uint8_t read = s->smb_addr & 0x01;
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uint8_t cmd = s->smb_cmd;
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uint8_t addr = s->smb_addr >> 1;
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i2c_bus *bus = s->smbus;
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#ifdef DEBUG
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printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
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#endif
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switch(prot) {
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case 0x0:
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smbus_quick_command(bus, addr, read);
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break;
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case 0x1:
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if (read) {
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s->smb_data0 = smbus_receive_byte(bus, addr);
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} else {
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smbus_send_byte(bus, addr, cmd);
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}
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break;
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case 0x2:
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if (read) {
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s->smb_data0 = smbus_read_byte(bus, addr, cmd);
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} else {
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smbus_write_byte(bus, addr, cmd, s->smb_data0);
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}
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break;
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case 0x3:
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if (read) {
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uint16_t val;
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val = smbus_read_word(bus, addr, cmd);
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s->smb_data0 = val;
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s->smb_data1 = val >> 8;
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} else {
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smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
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}
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break;
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case 0x5:
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if (read) {
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s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
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} else {
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smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
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}
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break;
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default:
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goto error;
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}
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return;
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error:
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s->smb_stat |= 0x04;
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}
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static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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PIIX4PMState *s = opaque;
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addr &= 0x3f;
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#ifdef DEBUG
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printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
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#endif
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switch(addr) {
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case SMBHSTSTS:
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s->smb_stat = 0;
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s->smb_index = 0;
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break;
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case SMBHSTCNT:
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s->smb_ctl = val;
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if (val & 0x40)
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smb_transaction(s);
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break;
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case SMBHSTCMD:
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s->smb_cmd = val;
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break;
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case SMBHSTADD:
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s->smb_addr = val;
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break;
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case SMBHSTDAT0:
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s->smb_data0 = val;
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break;
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case SMBHSTDAT1:
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s->smb_data1 = val;
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break;
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case SMBBLKDAT:
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s->smb_data[s->smb_index++] = val;
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if (s->smb_index > 31)
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s->smb_index = 0;
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break;
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default:
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break;
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}
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}
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static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
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{
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PIIX4PMState *s = opaque;
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uint32_t val;
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addr &= 0x3f;
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switch(addr) {
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case SMBHSTSTS:
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val = s->smb_stat;
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break;
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case SMBHSTCNT:
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s->smb_index = 0;
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val = s->smb_ctl & 0x1f;
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break;
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case SMBHSTCMD:
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val = s->smb_cmd;
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break;
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case SMBHSTADD:
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val = s->smb_addr;
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break;
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case SMBHSTDAT0:
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val = s->smb_data0;
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break;
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case SMBHSTDAT1:
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val = s->smb_data1;
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break;
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case SMBBLKDAT:
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val = s->smb_data[s->smb_index++];
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if (s->smb_index > 31)
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s->smb_index = 0;
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break;
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default:
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val = 0;
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break;
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}
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#ifdef DEBUG
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printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
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#endif
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return val;
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}
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static void pm_io_space_update(PIIX4PMState *s)
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{
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uint32_t pm_io_base;
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if (s->dev.config[0x80] & 1) {
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pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
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pm_io_base &= 0xffc0;
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/* XXX: need to improve memory and ioport allocation */
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#if defined(DEBUG)
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printf("PM: mapping to 0x%x\n", pm_io_base);
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#endif
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register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
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register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
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register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
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register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
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}
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}
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static void pm_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{
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pci_default_write_config(d, address, val, len);
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if (address == 0x80)
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pm_io_space_update((PIIX4PMState *)d);
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}
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|
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static void pm_save(QEMUFile* f,void *opaque)
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{
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PIIX4PMState *s = opaque;
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pci_device_save(&s->dev, f);
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qemu_put_be16s(f, &s->pmsts);
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qemu_put_be16s(f, &s->pmen);
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qemu_put_be16s(f, &s->pmcntrl);
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qemu_put_8s(f, &s->apmc);
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qemu_put_8s(f, &s->apms);
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qemu_put_timer(f, s->tmr_timer);
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qemu_put_be64(f, s->tmr_overflow_time);
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}
|
|
|
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static int pm_load(QEMUFile* f,void* opaque,int version_id)
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{
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PIIX4PMState *s = opaque;
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int ret;
|
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|
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if (version_id > 1)
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return -EINVAL;
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|
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ret = pci_device_load(&s->dev, f);
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if (ret < 0)
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return ret;
|
|
|
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qemu_get_be16s(f, &s->pmsts);
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qemu_get_be16s(f, &s->pmen);
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qemu_get_be16s(f, &s->pmcntrl);
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qemu_get_8s(f, &s->apmc);
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qemu_get_8s(f, &s->apms);
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qemu_get_timer(f, s->tmr_timer);
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s->tmr_overflow_time=qemu_get_be64(f);
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|
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pm_io_space_update(s);
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|
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return 0;
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}
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|
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static void piix4_reset(void *opaque)
|
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{
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PIIX4PMState *s = opaque;
|
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uint8_t *pci_conf = s->dev.config;
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|
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pci_conf[0x58] = 0;
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pci_conf[0x59] = 0;
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pci_conf[0x5a] = 0;
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pci_conf[0x5b] = 0;
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}
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|
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i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
|
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qemu_irq sci_irq)
|
|
{
|
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PIIX4PMState *s;
|
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uint8_t *pci_conf;
|
|
|
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s = (PIIX4PMState *)pci_register_device(bus,
|
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"PM", sizeof(PIIX4PMState),
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devfn, NULL, pm_write_config);
|
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pm_state = s;
|
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pci_conf = s->dev.config;
|
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pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
|
|
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
|
|
pci_conf[0x06] = 0x80;
|
|
pci_conf[0x07] = 0x02;
|
|
pci_conf[0x08] = 0x03; // revision number
|
|
pci_conf[0x09] = 0x00;
|
|
pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
|
|
pci_conf[0x0e] = 0x00; // header_type
|
|
pci_conf[0x3d] = 0x01; // interrupt pin 1
|
|
|
|
pci_conf[0x40] = 0x01; /* PM io base read only bit */
|
|
|
|
register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
|
|
register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
|
|
|
|
register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
|
|
|
|
if (kvm_enabled()) {
|
|
/* Mark SMM as already inited to prevent SMM from running. KVM does not
|
|
* support SMM mode. */
|
|
pci_conf[0x5B] = 0x02;
|
|
}
|
|
|
|
/* XXX: which specification is used ? The i82731AB has different
|
|
mappings */
|
|
pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
|
|
pci_conf[0x63] = 0x60;
|
|
pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
|
|
(serial_hds[1] != NULL ? 0x90 : 0);
|
|
|
|
pci_conf[0x90] = smb_io_base | 1;
|
|
pci_conf[0x91] = smb_io_base >> 8;
|
|
pci_conf[0xd2] = 0x09;
|
|
register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
|
|
register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
|
|
|
|
s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
|
|
|
|
register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
|
|
|
|
s->smbus = i2c_init_bus();
|
|
s->irq = sci_irq;
|
|
qemu_register_reset(piix4_reset, s);
|
|
|
|
return s->smbus;
|
|
}
|
|
|
|
#if defined(TARGET_I386)
|
|
void qemu_system_powerdown(void)
|
|
{
|
|
if (!pm_state) {
|
|
qemu_system_shutdown_request();
|
|
} else if (pm_state->pmen & PWRBTN_EN) {
|
|
pm_state->pmsts |= PWRBTN_EN;
|
|
pm_update_sci(pm_state);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#define GPE_BASE 0xafe0
|
|
#define PCI_BASE 0xae00
|
|
#define PCI_EJ_BASE 0xae08
|
|
|
|
struct gpe_regs {
|
|
uint16_t sts; /* status */
|
|
uint16_t en; /* enabled */
|
|
};
|
|
|
|
struct pci_status {
|
|
uint32_t up;
|
|
uint32_t down;
|
|
};
|
|
|
|
static struct gpe_regs gpe;
|
|
static struct pci_status pci0_status;
|
|
|
|
static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
|
|
{
|
|
if (addr & 1)
|
|
return (val >> 8) & 0xff;
|
|
return val & 0xff;
|
|
}
|
|
|
|
static uint32_t gpe_readb(void *opaque, uint32_t addr)
|
|
{
|
|
uint32_t val = 0;
|
|
struct gpe_regs *g = opaque;
|
|
switch (addr) {
|
|
case GPE_BASE:
|
|
case GPE_BASE + 1:
|
|
val = gpe_read_val(g->sts, addr);
|
|
break;
|
|
case GPE_BASE + 2:
|
|
case GPE_BASE + 3:
|
|
val = gpe_read_val(g->en, addr);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
#if defined(DEBUG)
|
|
printf("gpe read %lx == %lx\n", addr, val);
|
|
#endif
|
|
return val;
|
|
}
|
|
|
|
static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
|
|
{
|
|
if (addr & 1)
|
|
*cur = (*cur & 0xff) | (val << 8);
|
|
else
|
|
*cur = (*cur & 0xff00) | (val & 0xff);
|
|
}
|
|
|
|
static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
|
|
{
|
|
uint16_t x1, x0 = val & 0xff;
|
|
int shift = (addr & 1) ? 8 : 0;
|
|
|
|
x1 = (*cur >> shift) & 0xff;
|
|
|
|
x1 = x1 & ~x0;
|
|
|
|
*cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
|
|
}
|
|
|
|
static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
|
|
{
|
|
struct gpe_regs *g = opaque;
|
|
switch (addr) {
|
|
case GPE_BASE:
|
|
case GPE_BASE + 1:
|
|
gpe_reset_val(&g->sts, addr, val);
|
|
break;
|
|
case GPE_BASE + 2:
|
|
case GPE_BASE + 3:
|
|
gpe_write_val(&g->en, addr, val);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
#if defined(DEBUG)
|
|
printf("gpe write %lx <== %d\n", addr, val);
|
|
#endif
|
|
}
|
|
|
|
static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
|
|
{
|
|
uint32_t val = 0;
|
|
struct pci_status *g = opaque;
|
|
switch (addr) {
|
|
case PCI_BASE:
|
|
val = g->up;
|
|
break;
|
|
case PCI_BASE + 4:
|
|
val = g->down;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
#if defined(DEBUG)
|
|
printf("pcihotplug read %lx == %lx\n", addr, val);
|
|
#endif
|
|
return val;
|
|
}
|
|
|
|
static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
|
|
{
|
|
struct pci_status *g = opaque;
|
|
switch (addr) {
|
|
case PCI_BASE:
|
|
g->up = val;
|
|
break;
|
|
case PCI_BASE + 4:
|
|
g->down = val;
|
|
break;
|
|
}
|
|
|
|
#if defined(DEBUG)
|
|
printf("pcihotplug write %lx <== %d\n", addr, val);
|
|
#endif
|
|
}
|
|
|
|
static uint32_t pciej_read(void *opaque, uint32_t addr)
|
|
{
|
|
#if defined(DEBUG)
|
|
printf("pciej read %lx == %lx\n", addr, val);
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
|
|
{
|
|
#if defined (TARGET_I386)
|
|
int slot = ffs(val) - 1;
|
|
|
|
pci_device_hot_remove_success(0, slot);
|
|
#endif
|
|
|
|
#if defined(DEBUG)
|
|
printf("pciej write %lx <== %d\n", addr, val);
|
|
#endif
|
|
}
|
|
|
|
void qemu_system_hot_add_init(void)
|
|
{
|
|
register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe);
|
|
register_ioport_read(GPE_BASE, 4, 1, gpe_readb, &gpe);
|
|
|
|
register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status);
|
|
register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, &pci0_status);
|
|
|
|
register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, NULL);
|
|
register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, NULL);
|
|
}
|
|
|
|
static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot)
|
|
{
|
|
g->sts |= 2;
|
|
p->up |= (1 << slot);
|
|
}
|
|
|
|
static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot)
|
|
{
|
|
g->sts |= 2;
|
|
p->down |= (1 << slot);
|
|
}
|
|
|
|
void qemu_system_device_hot_add(int bus, int slot, int state)
|
|
{
|
|
pci0_status.up = 0;
|
|
pci0_status.down = 0;
|
|
if (state)
|
|
enable_device(&pci0_status, &gpe, slot);
|
|
else
|
|
disable_device(&pci0_status, &gpe, slot);
|
|
if (gpe.en & 2) {
|
|
qemu_set_irq(pm_state->irq, 1);
|
|
qemu_set_irq(pm_state->irq, 0);
|
|
}
|
|
}
|
|
|
|
struct acpi_table_header
|
|
{
|
|
char signature [4]; /* ACPI signature (4 ASCII characters) */
|
|
uint32_t length; /* Length of table, in bytes, including header */
|
|
uint8_t revision; /* ACPI Specification minor version # */
|
|
uint8_t checksum; /* To make sum of entire table == 0 */
|
|
char oem_id [6]; /* OEM identification */
|
|
char oem_table_id [8]; /* OEM table identification */
|
|
uint32_t oem_revision; /* OEM revision number */
|
|
char asl_compiler_id [4]; /* ASL compiler vendor ID */
|
|
uint32_t asl_compiler_revision; /* ASL compiler revision number */
|
|
} __attribute__((packed));
|
|
|
|
char *acpi_tables;
|
|
size_t acpi_tables_len;
|
|
|
|
static int acpi_checksum(const uint8_t *data, int len)
|
|
{
|
|
int sum, i;
|
|
sum = 0;
|
|
for(i = 0; i < len; i++)
|
|
sum += data[i];
|
|
return (-sum) & 0xff;
|
|
}
|
|
|
|
int acpi_table_add(const char *t)
|
|
{
|
|
static const char *dfl_id = "QEMUQEMU";
|
|
char buf[1024], *p, *f;
|
|
struct acpi_table_header acpi_hdr;
|
|
unsigned long val;
|
|
size_t off;
|
|
|
|
memset(&acpi_hdr, 0, sizeof(acpi_hdr));
|
|
|
|
if (get_param_value(buf, sizeof(buf), "sig", t)) {
|
|
strncpy(acpi_hdr.signature, buf, 4);
|
|
} else {
|
|
strncpy(acpi_hdr.signature, dfl_id, 4);
|
|
}
|
|
if (get_param_value(buf, sizeof(buf), "rev", t)) {
|
|
val = strtoul(buf, &p, 10);
|
|
if (val > 255 || *p != '\0')
|
|
goto out;
|
|
} else {
|
|
val = 1;
|
|
}
|
|
acpi_hdr.revision = (int8_t)val;
|
|
|
|
if (get_param_value(buf, sizeof(buf), "oem_id", t)) {
|
|
strncpy(acpi_hdr.oem_id, buf, 6);
|
|
} else {
|
|
strncpy(acpi_hdr.oem_id, dfl_id, 6);
|
|
}
|
|
|
|
if (get_param_value(buf, sizeof(buf), "oem_table_id", t)) {
|
|
strncpy(acpi_hdr.oem_table_id, buf, 8);
|
|
} else {
|
|
strncpy(acpi_hdr.oem_table_id, dfl_id, 8);
|
|
}
|
|
|
|
if (get_param_value(buf, sizeof(buf), "oem_rev", t)) {
|
|
val = strtol(buf, &p, 10);
|
|
if(*p != '\0')
|
|
goto out;
|
|
} else {
|
|
val = 1;
|
|
}
|
|
acpi_hdr.oem_revision = cpu_to_le32(val);
|
|
|
|
if (get_param_value(buf, sizeof(buf), "asl_compiler_id", t)) {
|
|
strncpy(acpi_hdr.asl_compiler_id, buf, 4);
|
|
} else {
|
|
strncpy(acpi_hdr.asl_compiler_id, dfl_id, 4);
|
|
}
|
|
|
|
if (get_param_value(buf, sizeof(buf), "asl_compiler_rev", t)) {
|
|
val = strtol(buf, &p, 10);
|
|
if(*p != '\0')
|
|
goto out;
|
|
} else {
|
|
val = 1;
|
|
}
|
|
acpi_hdr.asl_compiler_revision = cpu_to_le32(val);
|
|
|
|
if (!get_param_value(buf, sizeof(buf), "data", t)) {
|
|
buf[0] = '\0';
|
|
}
|
|
|
|
acpi_hdr.length = sizeof(acpi_hdr);
|
|
|
|
f = buf;
|
|
while (buf[0]) {
|
|
struct stat s;
|
|
char *n = index(f, ':');
|
|
if (n)
|
|
*n = '\0';
|
|
if(stat(f, &s) < 0) {
|
|
fprintf(stderr, "Can't stat file '%s': %s\n", f, strerror(errno));
|
|
goto out;
|
|
}
|
|
acpi_hdr.length += s.st_size;
|
|
if (!n)
|
|
break;
|
|
*n = ':';
|
|
f = n + 1;
|
|
}
|
|
|
|
if (!acpi_tables) {
|
|
acpi_tables_len = sizeof(uint16_t);
|
|
acpi_tables = qemu_mallocz(acpi_tables_len);
|
|
}
|
|
p = acpi_tables + acpi_tables_len;
|
|
acpi_tables_len += sizeof(uint16_t) + acpi_hdr.length;
|
|
acpi_tables = qemu_realloc(acpi_tables, acpi_tables_len);
|
|
|
|
acpi_hdr.length = cpu_to_le32(acpi_hdr.length);
|
|
*(uint16_t*)p = acpi_hdr.length;
|
|
p += sizeof(uint16_t);
|
|
memcpy(p, &acpi_hdr, sizeof(acpi_hdr));
|
|
off = sizeof(acpi_hdr);
|
|
|
|
f = buf;
|
|
while (buf[0]) {
|
|
struct stat s;
|
|
int fd;
|
|
char *n = index(f, ':');
|
|
if (n)
|
|
*n = '\0';
|
|
fd = open(f, O_RDONLY);
|
|
|
|
if(fd < 0)
|
|
goto out;
|
|
if(fstat(fd, &s) < 0) {
|
|
close(fd);
|
|
goto out;
|
|
}
|
|
|
|
do {
|
|
int r;
|
|
r = read(fd, p + off, s.st_size);
|
|
if (r > 0) {
|
|
off += r;
|
|
s.st_size -= r;
|
|
} else if ((r < 0 && errno != EINTR) || r == 0) {
|
|
close(fd);
|
|
goto out;
|
|
}
|
|
} while(s.st_size);
|
|
|
|
close(fd);
|
|
if (!n)
|
|
break;
|
|
f = n + 1;
|
|
}
|
|
|
|
((struct acpi_table_header*)p)->checksum = acpi_checksum((uint8_t*)p, off);
|
|
/* increase number of tables */
|
|
(*(uint16_t*)acpi_tables) =
|
|
cpu_to_le32(le32_to_cpu(*(uint16_t*)acpi_tables) + 1);
|
|
return 0;
|
|
out:
|
|
if (acpi_tables) {
|
|
free(acpi_tables);
|
|
acpi_tables = NULL;
|
|
}
|
|
return -1;
|
|
}
|