Anton Blanchard 8a94cfb05e tcg-ppc64: Fix RLDCL opcode ... The rldcl instruction doesn't have an sh field, so the minor opcode is shifted 1 bit. We were using the XO30 macro which shifted the minor opcode 2 bits. Remove XO30 and add MD30 and MDS30 macros which match the Power ISA categories. Cc: qemu-stable@nongnu.org Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Richard Henderson <rth@twiddle.net>		2013-06-17 10:41:52 -07:00
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tcg-target.c	tcg-ppc64: Fix RLDCL opcode	2013-06-17 10:41:52 -07:00
tcg-target.h	tcg-ppc64: Implement mulu2/muls2_i64	2013-04-15 20:09:54 +02:00