770c2fc7bb
The x86 vector instruction set is extremely irregular. With newer editions, Intel has filled in some of the blanks. However, we don't get many 64-bit operations until SSE4.2, introduced in 2009. The subsequent edition was for AVX1, introduced in 2011, which added three-operand addressing, and adjusts how all instructions should be encoded. Given the relatively narrow 2 year window between possible to support and desirable to support, and to vastly simplify code maintainence, I am only planning to support AVX1 and later cpus. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14 lines
540 B
C
14 lines
540 B
C
/* Target-specific opcodes for host vector expansion. These will be
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emitted by tcg_expand_vec_op. For those familiar with GCC internals,
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consider these to be UNSPEC with names. */
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DEF(x86_shufps_vec, 1, 2, 1, IMPLVEC)
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DEF(x86_vpblendvb_vec, 1, 3, 0, IMPLVEC)
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DEF(x86_blend_vec, 1, 2, 1, IMPLVEC)
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DEF(x86_packss_vec, 1, 2, 0, IMPLVEC)
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DEF(x86_packus_vec, 1, 2, 0, IMPLVEC)
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DEF(x86_psrldq_vec, 1, 1, 1, IMPLVEC)
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DEF(x86_vperm2i128_vec, 1, 2, 1, IMPLVEC)
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DEF(x86_punpckl_vec, 1, 2, 0, IMPLVEC)
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DEF(x86_punpckh_vec, 1, 2, 0, IMPLVEC)
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