The axidma irq orders are reversed in both the device model and the instantion. Undid both reversal (for no net change). Also needs to be reversed for consistency with Xilinx tools IRQ listing. Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
517 lines
13 KiB
C
517 lines
13 KiB
C
/*
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* QEMU model of Xilinx AXI-DMA block.
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*
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* Copyright (c) 2011 Edgar E. Iglesias.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "sysbus.h"
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#include "qemu-char.h"
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#include "qemu-timer.h"
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#include "ptimer.h"
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#include "qemu-log.h"
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#include "qdev-addr.h"
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#include "xilinx_axidma.h"
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#define D(x)
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#define R_DMACR (0x00 / 4)
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#define R_DMASR (0x04 / 4)
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#define R_CURDESC (0x08 / 4)
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#define R_TAILDESC (0x10 / 4)
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#define R_MAX (0x30 / 4)
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enum {
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DMACR_RUNSTOP = 1,
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DMACR_TAILPTR_MODE = 2,
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DMACR_RESET = 4
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};
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enum {
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DMASR_HALTED = 1,
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DMASR_IDLE = 2,
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DMASR_IOC_IRQ = 1 << 12,
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DMASR_DLY_IRQ = 1 << 13,
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DMASR_IRQ_MASK = 7 << 12
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};
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struct SDesc {
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uint64_t nxtdesc;
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uint64_t buffer_address;
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uint64_t reserved;
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uint32_t control;
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uint32_t status;
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uint32_t app[6];
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};
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enum {
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SDESC_CTRL_EOF = (1 << 26),
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SDESC_CTRL_SOF = (1 << 27),
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SDESC_CTRL_LEN_MASK = (1 << 23) - 1
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};
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enum {
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SDESC_STATUS_EOF = (1 << 26),
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SDESC_STATUS_SOF_BIT = 27,
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SDESC_STATUS_SOF = (1 << SDESC_STATUS_SOF_BIT),
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SDESC_STATUS_COMPLETE = (1 << 31)
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};
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struct AXIStream {
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QEMUBH *bh;
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ptimer_state *ptimer;
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qemu_irq irq;
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int nr;
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struct SDesc desc;
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int pos;
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unsigned int complete_cnt;
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uint32_t regs[R_MAX];
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};
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struct XilinxAXIDMA {
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SysBusDevice busdev;
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MemoryRegion iomem;
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uint32_t freqhz;
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void *dmach;
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struct AXIStream streams[2];
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};
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/*
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* Helper calls to extract info from desriptors and other trivial
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* state from regs.
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*/
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static inline int stream_desc_sof(struct SDesc *d)
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{
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return d->control & SDESC_CTRL_SOF;
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}
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static inline int stream_desc_eof(struct SDesc *d)
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{
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return d->control & SDESC_CTRL_EOF;
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}
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static inline int stream_resetting(struct AXIStream *s)
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{
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return !!(s->regs[R_DMACR] & DMACR_RESET);
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}
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static inline int stream_running(struct AXIStream *s)
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{
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return s->regs[R_DMACR] & DMACR_RUNSTOP;
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}
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static inline int stream_halted(struct AXIStream *s)
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{
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return s->regs[R_DMASR] & DMASR_HALTED;
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}
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static inline int stream_idle(struct AXIStream *s)
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{
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return !!(s->regs[R_DMASR] & DMASR_IDLE);
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}
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static void stream_reset(struct AXIStream *s)
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{
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s->regs[R_DMASR] = DMASR_HALTED; /* starts up halted. */
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s->regs[R_DMACR] = 1 << 16; /* Starts with one in compl threshold. */
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}
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/* Map an offset addr into a channel index. */
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static inline int streamid_from_addr(target_phys_addr_t addr)
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{
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int sid;
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sid = addr / (0x30);
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sid &= 1;
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return sid;
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}
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#ifdef DEBUG_ENET
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static void stream_desc_show(struct SDesc *d)
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{
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qemu_log("buffer_addr = " PRIx64 "\n", d->buffer_address);
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qemu_log("nxtdesc = " PRIx64 "\n", d->nxtdesc);
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qemu_log("control = %x\n", d->control);
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qemu_log("status = %x\n", d->status);
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}
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#endif
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static void stream_desc_load(struct AXIStream *s, target_phys_addr_t addr)
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{
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struct SDesc *d = &s->desc;
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int i;
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cpu_physical_memory_read(addr, (void *) d, sizeof *d);
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/* Convert from LE into host endianness. */
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d->buffer_address = le64_to_cpu(d->buffer_address);
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d->nxtdesc = le64_to_cpu(d->nxtdesc);
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d->control = le32_to_cpu(d->control);
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d->status = le32_to_cpu(d->status);
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for (i = 0; i < ARRAY_SIZE(d->app); i++) {
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d->app[i] = le32_to_cpu(d->app[i]);
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}
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}
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static void stream_desc_store(struct AXIStream *s, target_phys_addr_t addr)
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{
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struct SDesc *d = &s->desc;
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int i;
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/* Convert from host endianness into LE. */
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d->buffer_address = cpu_to_le64(d->buffer_address);
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d->nxtdesc = cpu_to_le64(d->nxtdesc);
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d->control = cpu_to_le32(d->control);
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d->status = cpu_to_le32(d->status);
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for (i = 0; i < ARRAY_SIZE(d->app); i++) {
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d->app[i] = cpu_to_le32(d->app[i]);
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}
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cpu_physical_memory_write(addr, (void *) d, sizeof *d);
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}
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static void stream_update_irq(struct AXIStream *s)
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{
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unsigned int pending, mask, irq;
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pending = s->regs[R_DMASR] & DMASR_IRQ_MASK;
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mask = s->regs[R_DMACR] & DMASR_IRQ_MASK;
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irq = pending & mask;
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qemu_set_irq(s->irq, !!irq);
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}
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static void stream_reload_complete_cnt(struct AXIStream *s)
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{
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unsigned int comp_th;
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comp_th = (s->regs[R_DMACR] >> 16) & 0xff;
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s->complete_cnt = comp_th;
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}
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static void timer_hit(void *opaque)
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{
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struct AXIStream *s = opaque;
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stream_reload_complete_cnt(s);
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s->regs[R_DMASR] |= DMASR_DLY_IRQ;
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stream_update_irq(s);
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}
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static void stream_complete(struct AXIStream *s)
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{
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unsigned int comp_delay;
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/* Start the delayed timer. */
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comp_delay = s->regs[R_DMACR] >> 24;
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if (comp_delay) {
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ptimer_stop(s->ptimer);
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ptimer_set_count(s->ptimer, comp_delay);
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ptimer_run(s->ptimer, 1);
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}
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s->complete_cnt--;
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if (s->complete_cnt == 0) {
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/* Raise the IOC irq. */
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s->regs[R_DMASR] |= DMASR_IOC_IRQ;
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stream_reload_complete_cnt(s);
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}
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}
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static void stream_process_mem2s(struct AXIStream *s,
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struct XilinxDMAConnection *dmach)
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{
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uint32_t prev_d;
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unsigned char txbuf[16 * 1024];
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unsigned int txlen;
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uint32_t app[6];
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if (!stream_running(s) || stream_idle(s)) {
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return;
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}
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while (1) {
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stream_desc_load(s, s->regs[R_CURDESC]);
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if (s->desc.status & SDESC_STATUS_COMPLETE) {
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s->regs[R_DMASR] |= DMASR_IDLE;
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break;
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}
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if (stream_desc_sof(&s->desc)) {
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s->pos = 0;
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memcpy(app, s->desc.app, sizeof app);
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}
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txlen = s->desc.control & SDESC_CTRL_LEN_MASK;
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if ((txlen + s->pos) > sizeof txbuf) {
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hw_error("%s: too small internal txbuf! %d\n", __func__,
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txlen + s->pos);
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}
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cpu_physical_memory_read(s->desc.buffer_address,
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txbuf + s->pos, txlen);
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s->pos += txlen;
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if (stream_desc_eof(&s->desc)) {
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xlx_dma_push_to_client(dmach, txbuf, s->pos, app);
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s->pos = 0;
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stream_complete(s);
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}
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/* Update the descriptor. */
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s->desc.status = txlen | SDESC_STATUS_COMPLETE;
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stream_desc_store(s, s->regs[R_CURDESC]);
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/* Advance. */
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prev_d = s->regs[R_CURDESC];
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s->regs[R_CURDESC] = s->desc.nxtdesc;
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if (prev_d == s->regs[R_TAILDESC]) {
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s->regs[R_DMASR] |= DMASR_IDLE;
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break;
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}
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}
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}
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static void stream_process_s2mem(struct AXIStream *s,
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unsigned char *buf, size_t len, uint32_t *app)
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{
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uint32_t prev_d;
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unsigned int rxlen;
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int pos = 0;
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int sof = 1;
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if (!stream_running(s) || stream_idle(s)) {
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return;
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}
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while (len) {
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stream_desc_load(s, s->regs[R_CURDESC]);
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if (s->desc.status & SDESC_STATUS_COMPLETE) {
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s->regs[R_DMASR] |= DMASR_IDLE;
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break;
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}
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rxlen = s->desc.control & SDESC_CTRL_LEN_MASK;
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if (rxlen > len) {
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/* It fits. */
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rxlen = len;
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}
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cpu_physical_memory_write(s->desc.buffer_address, buf + pos, rxlen);
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len -= rxlen;
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pos += rxlen;
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/* Update the descriptor. */
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if (!len) {
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int i;
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stream_complete(s);
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for (i = 0; i < 5; i++) {
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s->desc.app[i] = app[i];
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}
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s->desc.status |= SDESC_STATUS_EOF;
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}
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s->desc.status |= sof << SDESC_STATUS_SOF_BIT;
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s->desc.status |= SDESC_STATUS_COMPLETE;
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stream_desc_store(s, s->regs[R_CURDESC]);
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sof = 0;
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/* Advance. */
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prev_d = s->regs[R_CURDESC];
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s->regs[R_CURDESC] = s->desc.nxtdesc;
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if (prev_d == s->regs[R_TAILDESC]) {
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s->regs[R_DMASR] |= DMASR_IDLE;
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break;
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}
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}
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}
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static
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void axidma_push(void *opaque, unsigned char *buf, size_t len, uint32_t *app)
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{
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struct XilinxAXIDMA *d = opaque;
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struct AXIStream *s = &d->streams[1];
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if (!app) {
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hw_error("No stream app data!\n");
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}
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stream_process_s2mem(s, buf, len, app);
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stream_update_irq(s);
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}
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static uint64_t axidma_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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struct XilinxAXIDMA *d = opaque;
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struct AXIStream *s;
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uint32_t r = 0;
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int sid;
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sid = streamid_from_addr(addr);
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s = &d->streams[sid];
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addr = addr % 0x30;
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addr >>= 2;
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switch (addr) {
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case R_DMACR:
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/* Simulate one cycles reset delay. */
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s->regs[addr] &= ~DMACR_RESET;
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r = s->regs[addr];
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break;
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case R_DMASR:
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s->regs[addr] &= 0xffff;
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s->regs[addr] |= (s->complete_cnt & 0xff) << 16;
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s->regs[addr] |= (ptimer_get_count(s->ptimer) & 0xff) << 24;
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r = s->regs[addr];
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break;
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default:
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r = s->regs[addr];
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D(qemu_log("%s ch=%d addr=" TARGET_FMT_plx " v=%x\n",
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__func__, sid, addr * 4, r));
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break;
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}
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return r;
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}
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static void axidma_write(void *opaque, target_phys_addr_t addr,
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uint64_t value, unsigned size)
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{
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struct XilinxAXIDMA *d = opaque;
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struct AXIStream *s;
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int sid;
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sid = streamid_from_addr(addr);
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s = &d->streams[sid];
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addr = addr % 0x30;
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addr >>= 2;
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switch (addr) {
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case R_DMACR:
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/* Tailptr mode is always on. */
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value |= DMACR_TAILPTR_MODE;
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/* Remember our previous reset state. */
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value |= (s->regs[addr] & DMACR_RESET);
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s->regs[addr] = value;
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if (value & DMACR_RESET) {
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stream_reset(s);
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}
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if ((value & 1) && !stream_resetting(s)) {
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/* Start processing. */
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s->regs[R_DMASR] &= ~(DMASR_HALTED | DMASR_IDLE);
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}
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stream_reload_complete_cnt(s);
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break;
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case R_DMASR:
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/* Mask away write to clear irq lines. */
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value &= ~(value & DMASR_IRQ_MASK);
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s->regs[addr] = value;
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break;
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case R_TAILDESC:
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s->regs[addr] = value;
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s->regs[R_DMASR] &= ~DMASR_IDLE; /* Not idle. */
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if (!sid) {
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stream_process_mem2s(s, d->dmach);
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}
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break;
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default:
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D(qemu_log("%s: ch=%d addr=" TARGET_FMT_plx " v=%x\n",
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__func__, sid, addr * 4, value));
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s->regs[addr] = value;
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break;
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}
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stream_update_irq(s);
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}
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static const MemoryRegionOps axidma_ops = {
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.read = axidma_read,
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.write = axidma_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static int xilinx_axidma_init(SysBusDevice *dev)
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{
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struct XilinxAXIDMA *s = FROM_SYSBUS(typeof(*s), dev);
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int i;
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sysbus_init_irq(dev, &s->streams[0].irq);
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sysbus_init_irq(dev, &s->streams[1].irq);
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if (!s->dmach) {
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hw_error("Unconnected DMA channel.\n");
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}
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xlx_dma_connect_dma(s->dmach, s, axidma_push);
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memory_region_init_io(&s->iomem, &axidma_ops, s,
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"axidma", R_MAX * 4 * 2);
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sysbus_init_mmio(dev, &s->iomem);
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for (i = 0; i < 2; i++) {
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stream_reset(&s->streams[i]);
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s->streams[i].nr = i;
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s->streams[i].bh = qemu_bh_new(timer_hit, &s->streams[i]);
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s->streams[i].ptimer = ptimer_init(s->streams[i].bh);
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ptimer_set_freq(s->streams[i].ptimer, s->freqhz);
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}
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return 0;
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}
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static Property axidma_properties[] = {
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DEFINE_PROP_UINT32("freqhz", struct XilinxAXIDMA, freqhz, 50000000),
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DEFINE_PROP_PTR("dmach", struct XilinxAXIDMA, dmach),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void axidma_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = xilinx_axidma_init;
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dc->props = axidma_properties;
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}
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static TypeInfo axidma_info = {
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.name = "xilinx,axidma",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(struct XilinxAXIDMA),
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.class_init = axidma_class_init,
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};
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static void xilinx_axidma_register_types(void)
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{
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type_register_static(&axidma_info);
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}
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type_init(xilinx_axidma_register_types)
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