The following patch will need to handle properties registration during class_init time. Let's use a device_class_set_props() setter. spatch --macro-file scripts/cocci-macro-file.h --sp-file ./scripts/coccinelle/qdev-set-props.cocci --keep-comments --in-place --dir . @@ typedef DeviceClass; DeviceClass *d; expression val; @@ - d->props = val + device_class_set_props(d, val) Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200110153039.1379601-20-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
203 lines
5 KiB
C
203 lines
5 KiB
C
/*
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* ARM dummy L210, L220, PL310 cache controller.
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*
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* Copyright (c) 2010-2012 Calxeda
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or any later version, as published by the Free Software
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* Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include "qemu/osdep.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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/* L2C-310 r3p2 */
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#define CACHE_ID 0x410000c8
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#define TYPE_ARM_L2X0 "l2x0"
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#define ARM_L2X0(obj) OBJECT_CHECK(L2x0State, (obj), TYPE_ARM_L2X0)
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typedef struct L2x0State {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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uint32_t cache_type;
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uint32_t ctrl;
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uint32_t aux_ctrl;
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uint32_t data_ctrl;
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uint32_t tag_ctrl;
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uint32_t filter_start;
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uint32_t filter_end;
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} L2x0State;
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static const VMStateDescription vmstate_l2x0 = {
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.name = "l2x0",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(ctrl, L2x0State),
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VMSTATE_UINT32(aux_ctrl, L2x0State),
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VMSTATE_UINT32(data_ctrl, L2x0State),
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VMSTATE_UINT32(tag_ctrl, L2x0State),
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VMSTATE_UINT32(filter_start, L2x0State),
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VMSTATE_UINT32(filter_end, L2x0State),
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VMSTATE_END_OF_LIST()
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}
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};
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static uint64_t l2x0_priv_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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uint32_t cache_data;
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L2x0State *s = (L2x0State *)opaque;
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offset &= 0xfff;
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if (offset >= 0x730 && offset < 0x800) {
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return 0; /* cache ops complete */
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}
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switch (offset) {
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case 0:
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return CACHE_ID;
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case 0x4:
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/* aux_ctrl values affect cache_type values */
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cache_data = (s->aux_ctrl & (7 << 17)) >> 15;
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cache_data |= (s->aux_ctrl & (1 << 16)) >> 16;
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return s->cache_type |= (cache_data << 18) | (cache_data << 6);
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case 0x100:
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return s->ctrl;
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case 0x104:
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return s->aux_ctrl;
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case 0x108:
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return s->tag_ctrl;
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case 0x10C:
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return s->data_ctrl;
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case 0xC00:
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return s->filter_start;
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case 0xC04:
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return s->filter_end;
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case 0xF40:
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return 0;
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case 0xF60:
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return 0;
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case 0xF80:
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return 0;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"l2x0_priv_read: Bad offset %x\n", (int)offset);
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break;
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}
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return 0;
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}
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static void l2x0_priv_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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L2x0State *s = (L2x0State *)opaque;
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offset &= 0xfff;
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if (offset >= 0x730 && offset < 0x800) {
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/* ignore */
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return;
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}
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switch (offset) {
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case 0x100:
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s->ctrl = value & 1;
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break;
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case 0x104:
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s->aux_ctrl = value;
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break;
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case 0x108:
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s->tag_ctrl = value;
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break;
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case 0x10C:
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s->data_ctrl = value;
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break;
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case 0xC00:
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s->filter_start = value;
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break;
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case 0xC04:
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s->filter_end = value;
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break;
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case 0xF40:
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return;
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case 0xF60:
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return;
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case 0xF80:
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return;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"l2x0_priv_write: Bad offset %x\n", (int)offset);
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break;
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}
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}
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static void l2x0_priv_reset(DeviceState *dev)
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{
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L2x0State *s = ARM_L2X0(dev);
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s->ctrl = 0;
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s->aux_ctrl = 0x02020000;
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s->tag_ctrl = 0;
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s->data_ctrl = 0;
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s->filter_start = 0;
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s->filter_end = 0;
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}
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static const MemoryRegionOps l2x0_mem_ops = {
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.read = l2x0_priv_read,
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.write = l2x0_priv_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void l2x0_priv_init(Object *obj)
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{
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L2x0State *s = ARM_L2X0(obj);
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SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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memory_region_init_io(&s->iomem, obj, &l2x0_mem_ops, s,
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"l2x0_cc", 0x1000);
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sysbus_init_mmio(dev, &s->iomem);
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}
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static Property l2x0_properties[] = {
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DEFINE_PROP_UINT32("cache-type", L2x0State, cache_type, 0x1c100100),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void l2x0_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &vmstate_l2x0;
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device_class_set_props(dc, l2x0_properties);
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dc->reset = l2x0_priv_reset;
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}
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static const TypeInfo l2x0_info = {
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.name = TYPE_ARM_L2X0,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(L2x0State),
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.instance_init = l2x0_priv_init,
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.class_init = l2x0_class_init,
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};
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static void l2x0_register_types(void)
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{
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type_register_static(&l2x0_info);
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}
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type_init(l2x0_register_types)
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