Write mask is representing the bits we care about. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-11-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
296 lines
8.9 KiB
C
296 lines
8.9 KiB
C
/*
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* RISC-V Emulation Helpers for QEMU.
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "qemu/main-loop.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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/* Exceptions processing helpers */
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void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
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uint32_t exception, uintptr_t pc)
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{
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CPUState *cs = env_cpu(env);
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cs->exception_index = exception;
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cpu_loop_exit_restore(cs, pc);
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}
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void helper_raise_exception(CPURISCVState *env, uint32_t exception)
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{
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riscv_raise_exception(env, exception, 0);
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}
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target_ulong helper_csrr(CPURISCVState *env, int csr)
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{
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target_ulong val = 0;
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RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
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if (ret != RISCV_EXCP_NONE) {
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riscv_raise_exception(env, ret, GETPC());
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}
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return val;
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}
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void helper_csrw(CPURISCVState *env, int csr, target_ulong src)
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{
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target_ulong mask = env->xl == MXL_RV32 ? UINT32_MAX : (target_ulong)-1;
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RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask);
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if (ret != RISCV_EXCP_NONE) {
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riscv_raise_exception(env, ret, GETPC());
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}
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}
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target_ulong helper_csrrw(CPURISCVState *env, int csr,
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target_ulong src, target_ulong write_mask)
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{
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target_ulong val = 0;
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RISCVException ret = riscv_csrrw(env, csr, &val, src, write_mask);
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if (ret != RISCV_EXCP_NONE) {
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riscv_raise_exception(env, ret, GETPC());
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}
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return val;
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}
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target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
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{
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Int128 rv = int128_zero();
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RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
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int128_zero(),
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int128_zero());
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if (ret != RISCV_EXCP_NONE) {
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riscv_raise_exception(env, ret, GETPC());
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}
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env->retxh = int128_gethi(rv);
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return int128_getlo(rv);
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}
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void helper_csrw_i128(CPURISCVState *env, int csr,
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target_ulong srcl, target_ulong srch)
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{
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RISCVException ret = riscv_csrrw_i128(env, csr, NULL,
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int128_make128(srcl, srch),
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UINT128_MAX);
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if (ret != RISCV_EXCP_NONE) {
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riscv_raise_exception(env, ret, GETPC());
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}
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}
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target_ulong helper_csrrw_i128(CPURISCVState *env, int csr,
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target_ulong srcl, target_ulong srch,
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target_ulong maskl, target_ulong maskh)
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{
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Int128 rv = int128_zero();
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RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
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int128_make128(srcl, srch),
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int128_make128(maskl, maskh));
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if (ret != RISCV_EXCP_NONE) {
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riscv_raise_exception(env, ret, GETPC());
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}
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env->retxh = int128_gethi(rv);
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return int128_getlo(rv);
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}
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#ifndef CONFIG_USER_ONLY
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target_ulong helper_sret(CPURISCVState *env)
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{
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uint64_t mstatus;
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target_ulong prev_priv, prev_virt;
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if (!(env->priv >= PRV_S)) {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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}
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target_ulong retpc = env->sepc;
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if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
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riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
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}
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if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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}
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if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) &&
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get_field(env->hstatus, HSTATUS_VTSR)) {
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riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
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}
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mstatus = env->mstatus;
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if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
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/* We support Hypervisor extensions and virtulisation is disabled */
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target_ulong hstatus = env->hstatus;
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prev_priv = get_field(mstatus, MSTATUS_SPP);
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prev_virt = get_field(hstatus, HSTATUS_SPV);
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hstatus = set_field(hstatus, HSTATUS_SPV, 0);
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mstatus = set_field(mstatus, MSTATUS_SPP, 0);
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mstatus = set_field(mstatus, SSTATUS_SIE,
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get_field(mstatus, SSTATUS_SPIE));
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mstatus = set_field(mstatus, SSTATUS_SPIE, 1);
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env->mstatus = mstatus;
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env->hstatus = hstatus;
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if (prev_virt) {
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riscv_cpu_swap_hypervisor_regs(env);
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}
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riscv_cpu_set_virt_enabled(env, prev_virt);
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} else {
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prev_priv = get_field(mstatus, MSTATUS_SPP);
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mstatus = set_field(mstatus, MSTATUS_SIE,
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get_field(mstatus, MSTATUS_SPIE));
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mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
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mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
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env->mstatus = mstatus;
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}
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riscv_cpu_set_mode(env, prev_priv);
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return retpc;
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}
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target_ulong helper_mret(CPURISCVState *env)
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{
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if (!(env->priv >= PRV_M)) {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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}
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target_ulong retpc = env->mepc;
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if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
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riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
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}
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uint64_t mstatus = env->mstatus;
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target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
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if (riscv_feature(env, RISCV_FEATURE_PMP) &&
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!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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}
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target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
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mstatus = set_field(mstatus, MSTATUS_MIE,
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get_field(mstatus, MSTATUS_MPIE));
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mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
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mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
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mstatus = set_field(mstatus, MSTATUS_MPV, 0);
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env->mstatus = mstatus;
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riscv_cpu_set_mode(env, prev_priv);
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if (riscv_has_ext(env, RVH)) {
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if (prev_virt) {
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riscv_cpu_swap_hypervisor_regs(env);
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}
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riscv_cpu_set_virt_enabled(env, prev_virt);
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}
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return retpc;
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}
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void helper_wfi(CPURISCVState *env)
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{
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CPUState *cs = env_cpu(env);
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bool rvs = riscv_has_ext(env, RVS);
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bool prv_u = env->priv == PRV_U;
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bool prv_s = env->priv == PRV_S;
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if (((prv_s || (!rvs && prv_u)) && get_field(env->mstatus, MSTATUS_TW)) ||
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(rvs && prv_u && !riscv_cpu_virt_enabled(env))) {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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} else if (riscv_cpu_virt_enabled(env) && (prv_u ||
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(prv_s && get_field(env->hstatus, HSTATUS_VTW)))) {
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riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
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} else {
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cs->halted = 1;
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cs->exception_index = EXCP_HLT;
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cpu_loop_exit(cs);
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}
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}
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void helper_tlb_flush(CPURISCVState *env)
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{
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CPUState *cs = env_cpu(env);
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if (!(env->priv >= PRV_S) ||
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(env->priv == PRV_S &&
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get_field(env->mstatus, MSTATUS_TVM))) {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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} else if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) &&
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get_field(env->hstatus, HSTATUS_VTVM)) {
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riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
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} else {
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tlb_flush(cs);
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}
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}
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void helper_hyp_tlb_flush(CPURISCVState *env)
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{
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CPUState *cs = env_cpu(env);
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if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
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riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
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}
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if (env->priv == PRV_M ||
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(env->priv == PRV_S && !riscv_cpu_virt_enabled(env))) {
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tlb_flush(cs);
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return;
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}
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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}
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void helper_hyp_gvma_tlb_flush(CPURISCVState *env)
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{
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if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env) &&
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get_field(env->mstatus, MSTATUS_TVM)) {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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}
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helper_hyp_tlb_flush(env);
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}
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target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address)
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{
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int mmu_idx = cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
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return cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC());
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}
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target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address)
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{
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int mmu_idx = cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
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return cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC());
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}
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#endif /* !CONFIG_USER_ONLY */
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