3367c62f52
(Might need more patch splitting) Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190215170029.15641-12-clg@kaod.org> [dwg: Hack to fix compile with some earlier include tweaks of mine] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
62 lines
2 KiB
C
62 lines
2 KiB
C
/*
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* PowerPC ISAV3 BookS emulation generic mmu helpers for qemu.
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*
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* Copyright (c) 2017 Suraj Jitindar Singh, IBM Corporation
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "mmu-hash64.h"
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#include "mmu-book3s-v3.h"
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#include "mmu-radix64.h"
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int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
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int mmu_idx)
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{
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if (ppc64_v3_radix(cpu)) { /* Guest uses radix */
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return ppc_radix64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx);
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} else { /* Guest uses hash */
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return ppc_hash64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx);
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}
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}
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hwaddr ppc64_v3_get_phys_page_debug(PowerPCCPU *cpu, vaddr eaddr)
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{
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if (ppc64_v3_radix(cpu)) {
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return ppc_radix64_get_phys_page_debug(cpu, eaddr);
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} else {
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return ppc_hash64_get_phys_page_debug(cpu, eaddr);
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}
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}
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bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t *entry)
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{
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uint64_t patb = cpu->env.spr[SPR_PTCR] & PTCR_PATB;
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uint64_t pats = cpu->env.spr[SPR_PTCR] & PTCR_PATS;
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/* Calculate number of entries */
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pats = 1ull << (pats + 12 - 4);
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if (pats <= lpid) {
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return false;
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}
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/* Grab entry */
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patb += 16 * lpid;
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entry->dw0 = ldq_phys(CPU(cpu)->as, patb);
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entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8);
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return true;
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}
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