Increase the maximum number of GIC interrupts for a9mp and a11mp to 1020, and create a configurable property for each defaulting to 96 and 64 (respectively) so that device modelers can set the value appropriately for their SoC. Other ARM processors also set their maximum number of used IRQs appropriately. Set the maximum theoretical number of GIC interrupts to 1020 and update the save/restore code to only use the appropriate number for each SoC. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Reviewed-by: Andreas Färber <afaerber@suse.de> [Peter Maydell: fixed minor whitespace snafu] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
236 lines
7.3 KiB
C
236 lines
7.3 KiB
C
/*
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* Cortex-A9MPCore internal peripheral emulation.
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*
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* Copyright (c) 2009 CodeSourcery.
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* Copyright (c) 2011 Linaro Limited.
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* Written by Paul Brook, Peter Maydell.
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*
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* This code is licensed under the GPL.
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*/
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#include "sysbus.h"
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/* Configuration for arm_gic.c:
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* max number of CPUs, how to ID current CPU
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*/
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#define NCPU 4
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static inline int
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gic_get_current_cpu(void)
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{
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return cpu_single_env->cpu_index;
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}
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#include "arm_gic.c"
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/* A9MP private memory region. */
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typedef struct a9mp_priv_state {
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gic_state gic;
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uint32_t scu_control;
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uint32_t scu_status;
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uint32_t old_timer_status[8];
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uint32_t num_cpu;
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qemu_irq *timer_irq;
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MemoryRegion scu_iomem;
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MemoryRegion ptimer_iomem;
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MemoryRegion container;
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DeviceState *mptimer;
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uint32_t num_irq;
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} a9mp_priv_state;
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static uint64_t a9_scu_read(void *opaque, target_phys_addr_t offset,
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unsigned size)
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{
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a9mp_priv_state *s = (a9mp_priv_state *)opaque;
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switch (offset) {
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case 0x00: /* Control */
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return s->scu_control;
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case 0x04: /* Configuration */
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return (((1 << s->num_cpu) - 1) << 4) | (s->num_cpu - 1);
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case 0x08: /* CPU Power Status */
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return s->scu_status;
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case 0x09: /* CPU status. */
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return s->scu_status >> 8;
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case 0x0a: /* CPU status. */
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return s->scu_status >> 16;
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case 0x0b: /* CPU status. */
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return s->scu_status >> 24;
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case 0x0c: /* Invalidate All Registers In Secure State */
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return 0;
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case 0x40: /* Filtering Start Address Register */
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case 0x44: /* Filtering End Address Register */
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/* RAZ/WI, like an implementation with only one AXI master */
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return 0;
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case 0x50: /* SCU Access Control Register */
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case 0x54: /* SCU Non-secure Access Control Register */
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/* unimplemented, fall through */
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default:
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return 0;
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}
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}
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static void a9_scu_write(void *opaque, target_phys_addr_t offset,
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uint64_t value, unsigned size)
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{
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a9mp_priv_state *s = (a9mp_priv_state *)opaque;
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uint32_t mask;
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uint32_t shift;
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switch (size) {
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case 1:
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mask = 0xff;
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break;
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case 2:
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mask = 0xffff;
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break;
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case 4:
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mask = 0xffffffff;
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break;
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default:
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fprintf(stderr, "Invalid size %u in write to a9 scu register %x\n",
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size, offset);
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return;
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}
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switch (offset) {
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case 0x00: /* Control */
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s->scu_control = value & 1;
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break;
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case 0x4: /* Configuration: RO */
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break;
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case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */
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shift = (offset - 0x8) * 8;
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s->scu_status &= ~(mask << shift);
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s->scu_status |= ((value & mask) << shift);
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break;
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case 0x0c: /* Invalidate All Registers In Secure State */
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/* no-op as we do not implement caches */
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break;
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case 0x40: /* Filtering Start Address Register */
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case 0x44: /* Filtering End Address Register */
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/* RAZ/WI, like an implementation with only one AXI master */
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break;
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case 0x50: /* SCU Access Control Register */
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case 0x54: /* SCU Non-secure Access Control Register */
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/* unimplemented, fall through */
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default:
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break;
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}
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}
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static const MemoryRegionOps a9_scu_ops = {
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.read = a9_scu_read,
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.write = a9_scu_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void a9mpcore_timer_irq_handler(void *opaque, int irq, int level)
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{
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a9mp_priv_state *s = (a9mp_priv_state *)opaque;
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if (level && !s->old_timer_status[irq]) {
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gic_set_pending_private(&s->gic, irq >> 1, 29 + (irq & 1));
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}
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s->old_timer_status[irq] = level;
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}
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static void a9mp_priv_reset(DeviceState *dev)
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{
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a9mp_priv_state *s = FROM_SYSBUSGIC(a9mp_priv_state, sysbus_from_qdev(dev));
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int i;
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s->scu_control = 0;
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for (i = 0; i < ARRAY_SIZE(s->old_timer_status); i++) {
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s->old_timer_status[i] = 0;
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}
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}
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static int a9mp_priv_init(SysBusDevice *dev)
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{
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a9mp_priv_state *s = FROM_SYSBUSGIC(a9mp_priv_state, dev);
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SysBusDevice *busdev;
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int i;
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if (s->num_cpu > NCPU) {
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hw_error("a9mp_priv_init: num-cpu may not be more than %d\n", NCPU);
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}
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gic_init(&s->gic, s->num_cpu, s->num_irq);
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s->mptimer = qdev_create(NULL, "arm_mptimer");
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qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
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qdev_init_nofail(s->mptimer);
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busdev = sysbus_from_qdev(s->mptimer);
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/* Memory map (addresses are offsets from PERIPHBASE):
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* 0x0000-0x00ff -- Snoop Control Unit
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* 0x0100-0x01ff -- GIC CPU interface
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* 0x0200-0x02ff -- Global Timer
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* 0x0300-0x05ff -- nothing
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* 0x0600-0x06ff -- private timers and watchdogs
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* 0x0700-0x0fff -- nothing
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* 0x1000-0x1fff -- GIC Distributor
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*
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* We should implement the global timer but don't currently do so.
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*/
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memory_region_init(&s->container, "a9mp-priv-container", 0x2000);
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memory_region_init_io(&s->scu_iomem, &a9_scu_ops, s, "a9mp-scu", 0x100);
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memory_region_add_subregion(&s->container, 0, &s->scu_iomem);
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/* GIC CPU interface */
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memory_region_add_subregion(&s->container, 0x100, &s->gic.cpuiomem[0]);
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/* Note that the A9 exposes only the "timer/watchdog for this core"
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* memory region, not the "timer/watchdog for core X" ones 11MPcore has.
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*/
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memory_region_add_subregion(&s->container, 0x600,
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sysbus_mmio_get_region(busdev, 0));
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memory_region_add_subregion(&s->container, 0x620,
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sysbus_mmio_get_region(busdev, 1));
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memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);
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sysbus_init_mmio(dev, &s->container);
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/* Wire up the interrupt from each watchdog and timer. */
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s->timer_irq = qemu_allocate_irqs(a9mpcore_timer_irq_handler,
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s, (s->num_cpu + 1) * 2);
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for (i = 0; i < s->num_cpu * 2; i++) {
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sysbus_connect_irq(busdev, i, s->timer_irq[i]);
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}
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return 0;
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}
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static const VMStateDescription vmstate_a9mp_priv = {
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.name = "a9mpcore_priv",
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.version_id = 2,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(scu_control, a9mp_priv_state),
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VMSTATE_UINT32_ARRAY(old_timer_status, a9mp_priv_state, 8),
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VMSTATE_UINT32_V(scu_status, a9mp_priv_state, 2),
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VMSTATE_END_OF_LIST()
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}
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};
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static SysBusDeviceInfo a9mp_priv_info = {
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.init = a9mp_priv_init,
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.qdev.name = "a9mpcore_priv",
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.qdev.size = sizeof(a9mp_priv_state),
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.qdev.vmsd = &vmstate_a9mp_priv,
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.qdev.reset = a9mp_priv_reset,
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32("num-cpu", a9mp_priv_state, num_cpu, 1),
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/* The Cortex-A9MP may have anything from 0 to 224 external interrupt
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* IRQ lines (with another 32 internal). We default to 64+32, which
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* is the number provided by the Cortex-A9MP test chip in the
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* Realview PBX-A9 and Versatile Express A9 development boards.
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* Other boards may differ and should set this property appropriately.
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*/
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DEFINE_PROP_UINT32("num-irq", a9mp_priv_state, num_irq, 96),
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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static void a9mp_register_devices(void)
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{
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sysbus_register_withprop(&a9mp_priv_info);
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}
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device_init(a9mp_register_devices)
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