Split ARM on/off function from PSCI support code. This will allow to reuse these functions in other code. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
225 lines
6.5 KiB
C
225 lines
6.5 KiB
C
/*
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* QEMU support -- ARM Power Control specific functions.
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*
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* Copyright (c) 2016 Jean-Christophe Dubois
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include "qemu/osdep.h"
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#include <cpu.h>
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#include <cpu-qom.h>
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#include "internals.h"
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#include "arm-powerctl.h"
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#ifndef DEBUG_ARM_POWERCTL
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#define DEBUG_ARM_POWERCTL 0
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#endif
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#define DPRINTF(fmt, args...) \
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do { \
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if (DEBUG_ARM_POWERCTL) { \
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fprintf(stderr, "[ARM]%s: " fmt , __func__, ##args); \
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} \
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} while (0)
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CPUState *arm_get_cpu_by_id(uint64_t id)
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{
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CPUState *cpu;
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DPRINTF("cpu %" PRId64 "\n", id);
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CPU_FOREACH(cpu) {
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ARMCPU *armcpu = ARM_CPU(cpu);
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if (armcpu->mp_affinity == id) {
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return cpu;
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}
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}
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qemu_log_mask(LOG_GUEST_ERROR,
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"[ARM]%s: Requesting unknown CPU %" PRId64 "\n",
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__func__, id);
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return NULL;
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}
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int arm_set_cpu_on(uint64_t cpuid, uint64_t entry, uint64_t context_id,
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uint32_t target_el, bool target_aa64)
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{
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CPUState *target_cpu_state;
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ARMCPU *target_cpu;
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DPRINTF("cpu %" PRId64 " (EL %d, %s) @ 0x%" PRIx64 " with R0 = 0x%" PRIx64
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"\n", cpuid, target_el, target_aa64 ? "aarch64" : "aarch32", entry,
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context_id);
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/* requested EL level need to be in the 1 to 3 range */
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assert((target_el > 0) && (target_el < 4));
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if (target_aa64 && (entry & 3)) {
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/*
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* if we are booting in AArch64 mode then "entry" needs to be 4 bytes
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* aligned.
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*/
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return QEMU_ARM_POWERCTL_INVALID_PARAM;
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}
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/* Retrieve the cpu we are powering up */
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target_cpu_state = arm_get_cpu_by_id(cpuid);
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if (!target_cpu_state) {
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/* The cpu was not found */
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return QEMU_ARM_POWERCTL_INVALID_PARAM;
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}
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target_cpu = ARM_CPU(target_cpu_state);
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if (!target_cpu->powered_off) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"[ARM]%s: CPU %" PRId64 " is already on\n",
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__func__, cpuid);
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return QEMU_ARM_POWERCTL_ALREADY_ON;
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}
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/*
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* The newly brought CPU is requested to enter the exception level
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* "target_el" and be in the requested mode (AArch64 or AArch32).
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*/
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if (((target_el == 3) && !arm_feature(&target_cpu->env, ARM_FEATURE_EL3)) ||
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((target_el == 2) && !arm_feature(&target_cpu->env, ARM_FEATURE_EL2))) {
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/*
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* The CPU does not support requested level
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*/
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return QEMU_ARM_POWERCTL_INVALID_PARAM;
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}
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if (!target_aa64 && arm_feature(&target_cpu->env, ARM_FEATURE_AARCH64)) {
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/*
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* For now we don't support booting an AArch64 CPU in AArch32 mode
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* TODO: We should add this support later
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*/
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qemu_log_mask(LOG_UNIMP,
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"[ARM]%s: Starting AArch64 CPU %" PRId64
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" in AArch32 mode is not supported yet\n",
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__func__, cpuid);
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return QEMU_ARM_POWERCTL_INVALID_PARAM;
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}
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/* Initialize the cpu we are turning on */
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cpu_reset(target_cpu_state);
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target_cpu->powered_off = false;
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target_cpu_state->halted = 0;
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if (target_aa64) {
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if ((target_el < 3) && arm_feature(&target_cpu->env, ARM_FEATURE_EL3)) {
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/*
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* As target mode is AArch64, we need to set lower
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* exception level (the requested level 2) to AArch64
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*/
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target_cpu->env.cp15.scr_el3 |= SCR_RW;
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}
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if ((target_el < 2) && arm_feature(&target_cpu->env, ARM_FEATURE_EL2)) {
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/*
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* As target mode is AArch64, we need to set lower
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* exception level (the requested level 1) to AArch64
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*/
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target_cpu->env.cp15.hcr_el2 |= HCR_RW;
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}
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target_cpu->env.pstate = aarch64_pstate_mode(target_el, true);
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} else {
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/* We are requested to boot in AArch32 mode */
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static uint32_t mode_for_el[] = { 0,
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ARM_CPU_MODE_SVC,
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ARM_CPU_MODE_HYP,
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ARM_CPU_MODE_SVC };
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cpsr_write(&target_cpu->env, mode_for_el[target_el], CPSR_M,
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CPSRWriteRaw);
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}
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if (target_el == 3) {
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/* Processor is in secure mode */
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target_cpu->env.cp15.scr_el3 &= ~SCR_NS;
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} else {
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/* Processor is not in secure mode */
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target_cpu->env.cp15.scr_el3 |= SCR_NS;
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}
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/* We check if the started CPU is now at the correct level */
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assert(target_el == arm_current_el(&target_cpu->env));
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if (target_aa64) {
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target_cpu->env.xregs[0] = context_id;
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target_cpu->env.thumb = false;
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} else {
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target_cpu->env.regs[0] = context_id;
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target_cpu->env.thumb = entry & 1;
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entry &= 0xfffffffe;
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}
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/* Start the new CPU at the requested address */
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cpu_set_pc(target_cpu_state, entry);
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/* We are good to go */
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return QEMU_ARM_POWERCTL_RET_SUCCESS;
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}
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int arm_set_cpu_off(uint64_t cpuid)
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{
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CPUState *target_cpu_state;
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ARMCPU *target_cpu;
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DPRINTF("cpu %" PRId64 "\n", cpuid);
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/* change to the cpu we are powering up */
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target_cpu_state = arm_get_cpu_by_id(cpuid);
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if (!target_cpu_state) {
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return QEMU_ARM_POWERCTL_INVALID_PARAM;
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}
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target_cpu = ARM_CPU(target_cpu_state);
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if (target_cpu->powered_off) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"[ARM]%s: CPU %" PRId64 " is already off\n",
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__func__, cpuid);
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return QEMU_ARM_POWERCTL_IS_OFF;
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}
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target_cpu->powered_off = true;
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target_cpu_state->halted = 1;
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target_cpu_state->exception_index = EXCP_HLT;
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cpu_loop_exit(target_cpu_state);
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/* notreached */
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return QEMU_ARM_POWERCTL_RET_SUCCESS;
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}
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int arm_reset_cpu(uint64_t cpuid)
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{
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CPUState *target_cpu_state;
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ARMCPU *target_cpu;
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DPRINTF("cpu %" PRId64 "\n", cpuid);
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/* change to the cpu we are resetting */
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target_cpu_state = arm_get_cpu_by_id(cpuid);
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if (!target_cpu_state) {
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return QEMU_ARM_POWERCTL_INVALID_PARAM;
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}
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target_cpu = ARM_CPU(target_cpu_state);
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if (target_cpu->powered_off) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"[ARM]%s: CPU %" PRId64 " is off\n",
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__func__, cpuid);
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return QEMU_ARM_POWERCTL_IS_OFF;
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}
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/* Reset the cpu */
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cpu_reset(target_cpu_state);
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return QEMU_ARM_POWERCTL_RET_SUCCESS;
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}
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