git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3811 c046a42c-6fe2-441c-8c8c-71466251a162
318 lines
7.6 KiB
C
318 lines
7.6 KiB
C
/*
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* QEMU SCI/SCIF serial port emulation
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*
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* Copyright (c) 2007 Magnus Damm
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*
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* Based on serial.c - QEMU 16450 UART emulation
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "sh.h"
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#include "qemu-char.h"
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#include <assert.h>
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//#define DEBUG_SERIAL
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#define SH_SERIAL_FLAG_TEND (1 << 0)
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#define SH_SERIAL_FLAG_TDE (1 << 1)
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#define SH_SERIAL_FLAG_RDF (1 << 2)
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#define SH_SERIAL_FLAG_BRK (1 << 3)
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#define SH_SERIAL_FLAG_DR (1 << 4)
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typedef struct {
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uint8_t smr;
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uint8_t brr;
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uint8_t scr;
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uint8_t dr; /* ftdr / tdr */
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uint8_t sr; /* fsr / ssr */
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uint16_t fcr;
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uint8_t sptr;
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uint8_t rx_fifo[16]; /* frdr / rdr */
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uint8_t rx_cnt;
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target_phys_addr_t base;
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int freq;
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int feat;
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int flags;
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CharDriverState *chr;
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} sh_serial_state;
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static void sh_serial_ioport_write(void *opaque, uint32_t offs, uint32_t val)
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{
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sh_serial_state *s = opaque;
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unsigned char ch;
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#ifdef DEBUG_SERIAL
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printf("sh_serial: write base=0x%08lx offs=0x%02x val=0x%02x\n",
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(unsigned long) s->base, offs, val);
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#endif
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switch(offs) {
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case 0x00: /* SMR */
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s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
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return;
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case 0x04: /* BRR */
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s->brr = val;
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return;
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case 0x08: /* SCR */
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s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfb : 0xff);
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if (!(val & (1 << 5)))
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s->flags |= SH_SERIAL_FLAG_TEND;
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return;
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case 0x0c: /* FTDR / TDR */
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if (s->chr) {
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ch = val;
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qemu_chr_write(s->chr, &ch, 1);
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}
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s->dr = val;
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s->flags &= ~SH_SERIAL_FLAG_TDE;
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return;
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#if 0
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case 0x14: /* FRDR / RDR */
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ret = 0;
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break;
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#endif
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}
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if (s->feat & SH_SERIAL_FEAT_SCIF) {
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switch(offs) {
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case 0x10: /* FSR */
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if (!(val & (1 << 6)))
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s->flags &= ~SH_SERIAL_FLAG_TEND;
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if (!(val & (1 << 5)))
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s->flags &= ~SH_SERIAL_FLAG_TDE;
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if (!(val & (1 << 4)))
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s->flags &= ~SH_SERIAL_FLAG_BRK;
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if (!(val & (1 << 1)))
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s->flags &= ~SH_SERIAL_FLAG_RDF;
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if (!(val & (1 << 0)))
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s->flags &= ~SH_SERIAL_FLAG_DR;
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return;
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case 0x18: /* FCR */
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s->fcr = val;
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return;
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case 0x20: /* SPTR */
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s->sptr = val;
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return;
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case 0x24: /* LSR */
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return;
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}
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}
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else {
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#if 0
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switch(offs) {
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case 0x0c:
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ret = s->dr;
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break;
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case 0x10:
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ret = 0;
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break;
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case 0x1c:
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ret = s->sptr;
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break;
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}
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#endif
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}
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fprintf(stderr, "sh_serial: unsupported write to 0x%02x\n", offs);
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assert(0);
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}
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static uint32_t sh_serial_ioport_read(void *opaque, uint32_t offs)
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{
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sh_serial_state *s = opaque;
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uint32_t ret = ~0;
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#if 0
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switch(offs) {
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case 0x00:
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ret = s->smr;
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break;
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case 0x04:
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ret = s->brr;
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break;
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case 0x08:
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ret = s->scr;
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break;
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case 0x14:
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ret = 0;
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break;
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}
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#endif
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if (s->feat & SH_SERIAL_FEAT_SCIF) {
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switch(offs) {
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case 0x10: /* FSR */
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ret = 0;
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if (s->flags & SH_SERIAL_FLAG_TEND)
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ret |= (1 << 6);
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if (s->flags & SH_SERIAL_FLAG_TDE)
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ret |= (1 << 5);
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if (s->flags & SH_SERIAL_FLAG_BRK)
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ret |= (1 << 4);
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if (s->flags & SH_SERIAL_FLAG_RDF)
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ret |= (1 << 1);
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if (s->flags & SH_SERIAL_FLAG_DR)
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ret |= (1 << 0);
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if (s->scr & (1 << 5))
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s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND;
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break;
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#if 0
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case 0x18:
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ret = s->fcr;
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break;
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#endif
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case 0x1c:
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ret = s->rx_cnt;
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break;
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case 0x20:
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ret = s->sptr;
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break;
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case 0x24:
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ret = 0;
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break;
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}
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}
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else {
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#if 0
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switch(offs) {
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case 0x0c:
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ret = s->dr;
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break;
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case 0x10:
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ret = 0;
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break;
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case 0x1c:
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ret = s->sptr;
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break;
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}
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#endif
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}
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#ifdef DEBUG_SERIAL
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printf("sh_serial: read base=0x%08lx offs=0x%02x val=0x%x\n",
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(unsigned long) s->base, offs, ret);
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#endif
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if (ret & ~((1 << 16) - 1)) {
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fprintf(stderr, "sh_serial: unsupported read from 0x%02x\n", offs);
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assert(0);
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}
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return ret;
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}
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static int sh_serial_can_receive(sh_serial_state *s)
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{
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return 0;
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}
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static void sh_serial_receive_byte(sh_serial_state *s, int ch)
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{
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}
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static void sh_serial_receive_break(sh_serial_state *s)
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{
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}
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static int sh_serial_can_receive1(void *opaque)
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{
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sh_serial_state *s = opaque;
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return sh_serial_can_receive(s);
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}
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static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size)
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{
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sh_serial_state *s = opaque;
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sh_serial_receive_byte(s, buf[0]);
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}
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static void sh_serial_event(void *opaque, int event)
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{
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sh_serial_state *s = opaque;
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if (event == CHR_EVENT_BREAK)
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sh_serial_receive_break(s);
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}
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static uint32_t sh_serial_read (void *opaque, target_phys_addr_t addr)
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{
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sh_serial_state *s = opaque;
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return sh_serial_ioport_read(s, addr - s->base);
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}
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static void sh_serial_write (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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sh_serial_state *s = opaque;
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sh_serial_ioport_write(s, addr - s->base, value);
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}
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static CPUReadMemoryFunc *sh_serial_readfn[] = {
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&sh_serial_read,
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&sh_serial_read,
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&sh_serial_read,
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};
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static CPUWriteMemoryFunc *sh_serial_writefn[] = {
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&sh_serial_write,
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&sh_serial_write,
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&sh_serial_write,
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};
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void sh_serial_init (target_phys_addr_t base, int feat,
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uint32_t freq, CharDriverState *chr)
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{
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sh_serial_state *s;
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int s_io_memory;
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s = qemu_mallocz(sizeof(sh_serial_state));
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if (!s)
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return;
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s->base = base;
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s->feat = feat;
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s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;
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s->smr = 0;
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s->brr = 0xff;
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s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
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s->sptr = 0;
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if (feat & SH_SERIAL_FEAT_SCIF) {
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s->fcr = 0;
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}
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else {
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s->dr = 0xff;
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}
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s->rx_cnt = 0;
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s_io_memory = cpu_register_io_memory(0, sh_serial_readfn,
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sh_serial_writefn, s);
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cpu_register_physical_memory(base, 0x28, s_io_memory);
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s->chr = chr;
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if (chr)
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qemu_chr_add_handlers(chr, sh_serial_can_receive1, sh_serial_receive1,
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sh_serial_event, s);
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}
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