Make the list of MPS2 boards consistent in the phrasing of each entry, use the correct casing of "Arm", and move the mps2-an511 entry so the list is in numeric order. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200903202048.15370-4-peter.maydell@linaro.org
34 lines
1.4 KiB
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34 lines
1.4 KiB
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Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)
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================================================================================================================
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These board models all use Arm M-profile CPUs.
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The Arm MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
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FPGA but is otherwise the same as the 2). Since the CPU itself
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and most of the devices are in the FPGA, the details of the board
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as seen by the guest depend significantly on the FPGA image.
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QEMU models the following FPGA images:
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``mps2-an385``
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Cortex-M3 as documented in Arm Application Note AN385
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``mps2-an386``
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Cortex-M4 as documented in Arm Application Note AN386
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``mps2-an500``
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Cortex-M7 as documented in Arm Application Note AN500
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``mps2-an505``
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Cortex-M33 as documented in Arm Application Note AN505
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``mps2-an511``
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Cortex-M3 'DesignStart' as documented in Arm Application Note AN511
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``mps2-an521``
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Dual Cortex-M33 as documented in Arm Application Note AN521
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Differences between QEMU and real hardware:
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- AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to
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block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as
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if zbt_boot_ctrl is always zero)
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- QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest
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visible difference is that the LAN9118 doesn't support checksum
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offloading
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