qemu-patch-raspberry4/include/hw/i386
Prasad Singamsetty 92e5d85e83 intel-iommu: Redefine macros to enable supporting 48 bit address width
The current implementation of Intel IOMMU code only supports 39 bits
host/iova address width so number of macros use hard coded values based
on that. This patch is to redefine them so they can be used with
variable address widths. This patch doesn't add any new functionality
but enables adding support for 48 bit address width.

Signed-off-by: Prasad Singamsetty <prasad.singamsety@oracle.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-01-18 21:52:38 +02:00
..
apic-msidef.h i386/msi: Correct mask of destination ID in MSI address 2017-12-01 18:28:15 +02:00
apic.h apic: add function to apic that will be used by hvf 2017-12-22 15:01:19 +01:00
apic_internal.h Revert "apic: save apic_delivered flag" 2017-03-27 14:41:01 +02:00
ich9.h tco: do not generate an NMI 2017-04-05 17:23:52 +02:00
intel_iommu.h intel-iommu: Redefine macros to enable supporting 48 bit address width 2018-01-18 21:52:38 +02:00
ioapic.h Clean up decorations and whitespace around header guards 2016-07-12 16:20:46 +02:00
ioapic_internal.h x86: ioapic: add support for explicit EOI 2016-08-03 18:44:57 +02:00
pc.h target/i386: add clflushopt to "Skylake-Server" cpu model 2018-01-17 23:04:31 -02:00
topology.h pc: Add x86_topo_ids_from_apicid() 2016-07-20 11:58:44 -03:00
x86-iommu.h intel_iommu: remove X86_IOMMU_PCI_DEVFN_MAX 2017-12-22 01:42:03 +02:00