Bin Meng 933f73f13e hw/riscv: microchip_pfsoc: Connect DDR memory controller modules ... Connect DDR SGMII PHY module and CFG module to the PolarFire SoC. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1603863010-15807-4-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-11-03 07:17:23 -08:00
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boot.c	hw/riscv: Load the kernel after the firmware	2020-10-22 12:00:22 -07:00
Kconfig	hw/riscv: microchip_pfsoc: Connect DDR memory controller modules	2020-11-03 07:17:23 -08:00
meson.build	hw/riscv: Always build riscv_hart.c	2020-09-09 15:54:19 -07:00
microchip_pfsoc.c	hw/riscv: microchip_pfsoc: Connect DDR memory controller modules	2020-11-03 07:17:23 -08:00
numa.c	hw/riscv: Add helpers for RISC-V multi-socket NUMA machines	2020-08-25 09:11:35 -07:00
opentitan.c	hw/riscv: Load the kernel after the firmware	2020-10-22 12:00:22 -07:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
sifive_e.c	hw/riscv: Load the kernel after the firmware	2020-10-22 12:00:22 -07:00
sifive_u.c	hw/riscv: sifive_u: Allow passing custom DTB	2020-11-03 07:17:23 -08:00
spike.c	hw/riscv: Load the kernel after the firmware	2020-10-22 12:00:22 -07:00
virt.c	hw/riscv: virt: Allow passing custom DTB	2020-11-03 07:17:23 -08:00