94a7897c41
Add support for the Get Log Page command and basic implementations of
the mandatory Error Information, SMART / Health Information and Firmware
Slot Information log pages.
In violation of the specification, the SMART / Health Information log
page does not persist information over the lifetime of the controller
because the device has no place to store such persistent state.
Note that the LPA field in the Identify Controller data structure
intentionally has bit 0 cleared because there is no namespace specific
information in the SMART / Health information log page.
Required for compliance with NVMe revision 1.3d. See NVM Express 1.3d,
Section 5.14 ("Get Log Page command").
Signed-off-by: Klaus Jensen <klaus.jensen@cnexlabs.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Acked-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Dmitry Fomichev <dmitry.fomichev@wdc.com>
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
Message-Id: <20200706061303.246057-8-its@irrelevant.dk>
122 lines
3 KiB
C
122 lines
3 KiB
C
#ifndef HW_NVME_H
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#define HW_NVME_H
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#include "block/nvme.h"
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typedef struct NvmeParams {
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char *serial;
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uint32_t num_queues; /* deprecated since 5.1 */
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uint32_t max_ioqpairs;
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uint16_t msix_qsize;
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uint32_t cmb_size_mb;
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} NvmeParams;
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typedef struct NvmeAsyncEvent {
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QSIMPLEQ_ENTRY(NvmeAsyncEvent) entry;
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NvmeAerResult result;
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} NvmeAsyncEvent;
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typedef struct NvmeRequest {
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struct NvmeSQueue *sq;
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BlockAIOCB *aiocb;
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uint16_t status;
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bool has_sg;
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NvmeCqe cqe;
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BlockAcctCookie acct;
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QEMUSGList qsg;
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QEMUIOVector iov;
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QTAILQ_ENTRY(NvmeRequest)entry;
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} NvmeRequest;
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typedef struct NvmeSQueue {
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struct NvmeCtrl *ctrl;
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uint16_t sqid;
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uint16_t cqid;
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uint32_t head;
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uint32_t tail;
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uint32_t size;
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uint64_t dma_addr;
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QEMUTimer *timer;
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NvmeRequest *io_req;
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QTAILQ_HEAD(, NvmeRequest) req_list;
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QTAILQ_HEAD(, NvmeRequest) out_req_list;
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QTAILQ_ENTRY(NvmeSQueue) entry;
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} NvmeSQueue;
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typedef struct NvmeCQueue {
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struct NvmeCtrl *ctrl;
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uint8_t phase;
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uint16_t cqid;
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uint16_t irq_enabled;
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uint32_t head;
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uint32_t tail;
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uint32_t vector;
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uint32_t size;
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uint64_t dma_addr;
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QEMUTimer *timer;
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QTAILQ_HEAD(, NvmeSQueue) sq_list;
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QTAILQ_HEAD(, NvmeRequest) req_list;
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} NvmeCQueue;
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typedef struct NvmeNamespace {
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NvmeIdNs id_ns;
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} NvmeNamespace;
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static inline NvmeLBAF *nvme_ns_lbaf(NvmeNamespace *ns)
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{
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NvmeIdNs *id_ns = &ns->id_ns;
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return &id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(id_ns->flbas)];
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}
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static inline uint8_t nvme_ns_lbads(NvmeNamespace *ns)
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{
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return nvme_ns_lbaf(ns)->ds;
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}
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#define TYPE_NVME "nvme"
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#define NVME(obj) \
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OBJECT_CHECK(NvmeCtrl, (obj), TYPE_NVME)
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typedef struct NvmeCtrl {
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PCIDevice parent_obj;
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MemoryRegion iomem;
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MemoryRegion ctrl_mem;
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NvmeBar bar;
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BlockConf conf;
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NvmeParams params;
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uint32_t page_size;
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uint16_t page_bits;
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uint16_t max_prp_ents;
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uint16_t cqe_size;
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uint16_t sqe_size;
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uint32_t reg_size;
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uint32_t num_namespaces;
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uint32_t max_q_ents;
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uint64_t ns_size;
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uint8_t *cmbuf;
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uint32_t irq_status;
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uint64_t host_timestamp; /* Timestamp sent by the host */
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uint64_t timestamp_set_qemu_clock_ms; /* QEMU clock time */
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uint64_t starttime_ms;
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uint16_t temperature;
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HostMemoryBackend *pmrdev;
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NvmeNamespace *namespaces;
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NvmeSQueue **sq;
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NvmeCQueue **cq;
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NvmeSQueue admin_sq;
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NvmeCQueue admin_cq;
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NvmeIdCtrl id_ctrl;
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NvmeFeatureVal features;
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} NvmeCtrl;
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/* calculate the number of LBAs that the namespace can accomodate */
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static inline uint64_t nvme_ns_nlbas(NvmeCtrl *n, NvmeNamespace *ns)
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{
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return n->ns_size >> nvme_ns_lbads(ns);
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}
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#endif /* HW_NVME_H */
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