This commit implements the single-byte mode of the SMBus. Each Nuvoton SoC has 16 System Management Bus (SMBus). These buses compliant with SMBus and I2C protocol. This patch implements the single-byte mode of the SMBus. In this mode, the user sends or receives a byte each time. The SMBus device transmits it to the underlying i2c device and sends an interrupt back to the QEMU guest. Reviewed-by: Doug Evans<dje@google.com> Reviewed-by: Tyrong Ting<kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Corey Minyard <cminyard@mvista.com> Message-id: 20210210220426.3577804-2-wuhaotsh@google.com Acked-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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arm_sbcon_i2c.h | ||
aspeed_i2c.h | ||
bitbang_i2c.h | ||
i2c.h | ||
imx_i2c.h | ||
microbit_i2c.h | ||
npcm7xx_smbus.h | ||
pm_smbus.h | ||
ppc4xx_i2c.h | ||
smbus_eeprom.h | ||
smbus_master.h | ||
smbus_slave.h |