a9321a4d49
This patch implements Supervisor Mode Execution Prevention (SMEP) and Supervisor Mode Access Prevention (SMAP) for x86. The purpose of the patch, obviously, is to help kernel developers debug the support for those features. A fair bit of the code relates to the handling of CPUID features. The CPUID code probably would get greatly simplified if all the feature bit words were unified into a single vector object, but in the interest of producing a minimal patch for SMEP/SMAP, and because I had very limited time for this project, I followed the existing style. [ v2: don't change the definition of the qemu64 CPU shorthand, since that breaks loading old snapshots. Per Anthony Liguori this can be fixed once the CPU feature set is snapshot. Change the coding style slightly to conform to checkpatch.pl. ] Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
391 lines
8.9 KiB
C
391 lines
8.9 KiB
C
/*
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* x86 condition code helpers
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "helper.h"
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const uint8_t parity_table[256] = {
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CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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};
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#define SHIFT 0
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#include "cc_helper_template.h"
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#undef SHIFT
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#define SHIFT 1
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#include "cc_helper_template.h"
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#undef SHIFT
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#define SHIFT 2
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#include "cc_helper_template.h"
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#undef SHIFT
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#ifdef TARGET_X86_64
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#define SHIFT 3
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#include "cc_helper_template.h"
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#undef SHIFT
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#endif
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static int compute_all_eflags(CPUX86State *env)
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{
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return CC_SRC;
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}
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static int compute_c_eflags(CPUX86State *env)
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{
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return CC_SRC & CC_C;
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}
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uint32_t helper_cc_compute_all(CPUX86State *env, int op)
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{
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switch (op) {
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default: /* should never happen */
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return 0;
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case CC_OP_EFLAGS:
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return compute_all_eflags(env);
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case CC_OP_MULB:
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return compute_all_mulb(env);
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case CC_OP_MULW:
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return compute_all_mulw(env);
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case CC_OP_MULL:
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return compute_all_mull(env);
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case CC_OP_ADDB:
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return compute_all_addb(env);
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case CC_OP_ADDW:
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return compute_all_addw(env);
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case CC_OP_ADDL:
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return compute_all_addl(env);
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case CC_OP_ADCB:
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return compute_all_adcb(env);
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case CC_OP_ADCW:
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return compute_all_adcw(env);
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case CC_OP_ADCL:
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return compute_all_adcl(env);
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case CC_OP_SUBB:
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return compute_all_subb(env);
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case CC_OP_SUBW:
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return compute_all_subw(env);
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case CC_OP_SUBL:
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return compute_all_subl(env);
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case CC_OP_SBBB:
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return compute_all_sbbb(env);
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case CC_OP_SBBW:
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return compute_all_sbbw(env);
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case CC_OP_SBBL:
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return compute_all_sbbl(env);
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case CC_OP_LOGICB:
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return compute_all_logicb(env);
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case CC_OP_LOGICW:
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return compute_all_logicw(env);
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case CC_OP_LOGICL:
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return compute_all_logicl(env);
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case CC_OP_INCB:
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return compute_all_incb(env);
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case CC_OP_INCW:
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return compute_all_incw(env);
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case CC_OP_INCL:
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return compute_all_incl(env);
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case CC_OP_DECB:
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return compute_all_decb(env);
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case CC_OP_DECW:
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return compute_all_decw(env);
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case CC_OP_DECL:
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return compute_all_decl(env);
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case CC_OP_SHLB:
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return compute_all_shlb(env);
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case CC_OP_SHLW:
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return compute_all_shlw(env);
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case CC_OP_SHLL:
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return compute_all_shll(env);
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case CC_OP_SARB:
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return compute_all_sarb(env);
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case CC_OP_SARW:
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return compute_all_sarw(env);
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case CC_OP_SARL:
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return compute_all_sarl(env);
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#ifdef TARGET_X86_64
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case CC_OP_MULQ:
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return compute_all_mulq(env);
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case CC_OP_ADDQ:
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return compute_all_addq(env);
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case CC_OP_ADCQ:
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return compute_all_adcq(env);
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case CC_OP_SUBQ:
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return compute_all_subq(env);
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case CC_OP_SBBQ:
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return compute_all_sbbq(env);
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case CC_OP_LOGICQ:
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return compute_all_logicq(env);
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case CC_OP_INCQ:
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return compute_all_incq(env);
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case CC_OP_DECQ:
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return compute_all_decq(env);
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case CC_OP_SHLQ:
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return compute_all_shlq(env);
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case CC_OP_SARQ:
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return compute_all_sarq(env);
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#endif
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}
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}
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uint32_t cpu_cc_compute_all(CPUX86State *env, int op)
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{
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return helper_cc_compute_all(env, op);
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}
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uint32_t helper_cc_compute_c(CPUX86State *env, int op)
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{
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switch (op) {
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default: /* should never happen */
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return 0;
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case CC_OP_EFLAGS:
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return compute_c_eflags(env);
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case CC_OP_MULB:
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return compute_c_mull(env);
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case CC_OP_MULW:
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return compute_c_mull(env);
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case CC_OP_MULL:
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return compute_c_mull(env);
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case CC_OP_ADDB:
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return compute_c_addb(env);
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case CC_OP_ADDW:
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return compute_c_addw(env);
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case CC_OP_ADDL:
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return compute_c_addl(env);
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case CC_OP_ADCB:
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return compute_c_adcb(env);
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case CC_OP_ADCW:
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return compute_c_adcw(env);
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case CC_OP_ADCL:
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return compute_c_adcl(env);
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case CC_OP_SUBB:
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return compute_c_subb(env);
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case CC_OP_SUBW:
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return compute_c_subw(env);
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case CC_OP_SUBL:
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return compute_c_subl(env);
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case CC_OP_SBBB:
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return compute_c_sbbb(env);
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case CC_OP_SBBW:
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return compute_c_sbbw(env);
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case CC_OP_SBBL:
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return compute_c_sbbl(env);
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case CC_OP_LOGICB:
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return compute_c_logicb();
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case CC_OP_LOGICW:
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return compute_c_logicw();
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case CC_OP_LOGICL:
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return compute_c_logicl();
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case CC_OP_INCB:
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return compute_c_incl(env);
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case CC_OP_INCW:
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return compute_c_incl(env);
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case CC_OP_INCL:
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return compute_c_incl(env);
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case CC_OP_DECB:
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return compute_c_incl(env);
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case CC_OP_DECW:
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return compute_c_incl(env);
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case CC_OP_DECL:
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return compute_c_incl(env);
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case CC_OP_SHLB:
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return compute_c_shlb(env);
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case CC_OP_SHLW:
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return compute_c_shlw(env);
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case CC_OP_SHLL:
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return compute_c_shll(env);
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case CC_OP_SARB:
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return compute_c_sarl(env);
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case CC_OP_SARW:
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return compute_c_sarl(env);
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case CC_OP_SARL:
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return compute_c_sarl(env);
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#ifdef TARGET_X86_64
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case CC_OP_MULQ:
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return compute_c_mull(env);
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case CC_OP_ADDQ:
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return compute_c_addq(env);
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case CC_OP_ADCQ:
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return compute_c_adcq(env);
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case CC_OP_SUBQ:
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return compute_c_subq(env);
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case CC_OP_SBBQ:
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return compute_c_sbbq(env);
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case CC_OP_LOGICQ:
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return compute_c_logicq();
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case CC_OP_INCQ:
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return compute_c_incl(env);
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case CC_OP_DECQ:
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return compute_c_incl(env);
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case CC_OP_SHLQ:
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return compute_c_shlq(env);
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case CC_OP_SARQ:
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return compute_c_sarl(env);
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#endif
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}
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}
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void helper_write_eflags(CPUX86State *env, target_ulong t0,
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uint32_t update_mask)
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{
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cpu_load_eflags(env, t0, update_mask);
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}
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target_ulong helper_read_eflags(CPUX86State *env)
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{
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uint32_t eflags;
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eflags = helper_cc_compute_all(env, CC_OP);
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eflags |= (DF & DF_MASK);
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eflags |= env->eflags & ~(VM_MASK | RF_MASK);
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return eflags;
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}
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void helper_clts(CPUX86State *env)
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{
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env->cr[0] &= ~CR0_TS_MASK;
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env->hflags &= ~HF_TS_MASK;
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}
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void helper_reset_rf(CPUX86State *env)
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{
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env->eflags &= ~RF_MASK;
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}
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void helper_cli(CPUX86State *env)
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{
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env->eflags &= ~IF_MASK;
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}
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void helper_sti(CPUX86State *env)
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{
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env->eflags |= IF_MASK;
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}
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void helper_clac(CPUX86State *env)
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{
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env->eflags &= ~AC_MASK;
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}
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void helper_stac(CPUX86State *env)
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{
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env->eflags |= AC_MASK;
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}
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#if 0
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/* vm86plus instructions */
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void helper_cli_vm(CPUX86State *env)
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{
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env->eflags &= ~VIF_MASK;
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}
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void helper_sti_vm(CPUX86State *env)
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{
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env->eflags |= VIF_MASK;
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if (env->eflags & VIP_MASK) {
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raise_exception(env, EXCP0D_GPF);
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}
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}
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#endif
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void helper_set_inhibit_irq(CPUX86State *env)
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{
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env->hflags |= HF_INHIBIT_IRQ_MASK;
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}
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void helper_reset_inhibit_irq(CPUX86State *env)
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{
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env->hflags &= ~HF_INHIBIT_IRQ_MASK;
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}
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