qemu-patch-raspberry4/include/exec
Haozhong Zhang 9837684316 hostmem-file: add "align" option
When mmap(2) the backend files, QEMU uses the host page size
(getpagesize(2)) by default as the alignment of mapping address.
However, some backends may require alignments different than the page
size. For example, mmap a device DAX (e.g., /dev/dax0.0) on Linux
kernel 4.13 to an address, which is 4K-aligned but not 2M-aligned,
fails with a kernel message like

[617494.969768] dax dax0.0: qemu-system-x86: dax_mmap: fail, unaligned vma (0x7fa37c579000 - 0x7fa43c579000, 0x1fffff)

Because there is no common approach to get such alignment requirement,
we add the 'align' option to 'memory-backend-file', so that users or
management utils, which have enough knowledge about the backend, can
specify a proper alignment via this option.

Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
Message-Id: <20171211072806.2812-2-haozhong.zhang@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
[ehabkost: fixed typo, fixed error_setg() format string]
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-01-19 11:18:51 -02:00
..
user linux-user: Use correct alignment for long long on i386 guests 2016-08-04 16:34:59 +03:00
address-spaces.h Clean up header guards that don't match their file name 2016-07-12 16:19:16 +02:00
cpu-all.h accel/tcg: allow to invalidate a write TLB entry immediately 2017-10-20 13:32:10 +02:00
cpu-common.h cpu: Introduce a wrapper for tlb_flush() that can be used in common code 2017-07-04 14:30:03 +02:00
cpu-defs.h cputlb: bring back tlb_flush_count under !TLB_DEBUG 2017-10-10 07:37:10 -07:00
cpu_ldst.h tcg: Record code_gen_buffer address for user-only memory helpers 2017-11-15 10:33:27 +01:00
cpu_ldst_template.h trace: switch to modular code generation for sub-directories 2017-01-31 17:11:18 +00:00
cpu_ldst_useronly_template.h tcg: Record code_gen_buffer address for user-only memory helpers 2017-11-15 10:33:27 +01:00
cputlb.h cputlb: bring back tlb_flush_count under !TLB_DEBUG 2017-10-10 07:37:10 -07:00
exec-all.h cpu: refactor cpu_address_space_init() 2017-12-21 09:30:31 +01:00
gdbstub.h gdbstub: rename cpu_index -> cpu_gdb_index 2017-07-14 12:04:41 +02:00
gen-icount.h tcg: Dynamically allocate TCGOps 2017-12-29 12:43:39 -08:00
helper-gen.h tcg: Allow 6 arguments to TCG helpers 2017-12-29 12:43:40 -08:00
helper-head.h tcg: Allow 6 arguments to TCG helpers 2017-12-29 12:43:40 -08:00
helper-proto.h tcg: Allow 6 arguments to TCG helpers 2017-12-29 12:43:40 -08:00
helper-tcg.h tcg: Allow 6 arguments to TCG helpers 2017-12-29 12:43:40 -08:00
hwaddr.h hw: Clean up includes 2016-06-07 18:19:23 +03:00
ioport.h hw: clean up hw/hw.h includes 2016-05-19 16:42:30 +02:00
log.h disas: Remove unused flags arguments 2017-10-25 11:55:09 +02:00
memattrs.h memory.h: Move MemTxResult type to memattrs.h 2017-09-04 15:21:54 +01:00
memory-internal.h exec.c: Factor out before/after actions for notdirty memory writes 2017-11-21 12:09:25 +00:00
memory.h hostmem-file: add "align" option 2018-01-19 11:18:51 -02:00
poison.h include/exec/poison: Mark CONFIG_SOFTMMU as poisoned 2017-07-04 14:39:11 +02:00
ram_addr.h cpu_physical_memory_sync_dirty_bitmap: Another alignment fix 2018-01-16 14:54:52 +01:00
ramlist.h ramblock: add new hmp command "info ramblock" 2017-05-17 17:31:16 +01:00
semihost.h semihosting: add --semihosting-config arg sub-argument 2015-06-19 14:17:45 +01:00
softmmu-semi.h Clean up decorations and whitespace around header guards 2016-07-12 16:20:46 +02:00
target_page.h migration: Make savevm.c target independent 2017-05-18 19:21:00 +02:00
tb-context.h tcg: take tb_ctx out of TCGContext 2017-10-24 13:53:42 -07:00
tb-hash-xx.h tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK 2017-10-24 13:53:41 -07:00
tb-hash.h tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK 2017-10-24 13:53:41 -07:00
tb-lookup.h tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK 2017-10-24 13:53:41 -07:00
translator.h tcg: Add generic translation framework 2017-09-06 08:06:47 -07:00