b5ff0c6183
Wire up the sysclk and refclk for the stm32f100 SoC. This SoC always runs the systick refclk at 1/8 the frequency of the main CPU clock, so the board code only needs to provide a single sysclk clock. Because there is only one board using this SoC, we convert the SoC and the board together, rather than splitting it into "add clock to SoC; connect clock in board; add error check in SoC code that clock is wired up". When the systick device starts honouring its clock inputs, this will fix an emulation inaccuracy in the stm32vldiscovery board where the systick reference clock was running at 1MHz rather than 3MHz. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-12-peter.maydell@linaro.org
66 lines
2 KiB
C
66 lines
2 KiB
C
/*
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* STM32F100 SoC
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*
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* Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_ARM_STM32F100_SOC_H
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#define HW_ARM_STM32F100_SOC_H
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#include "hw/char/stm32f2xx_usart.h"
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#include "hw/ssi/stm32f2xx_spi.h"
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#include "hw/arm/armv7m.h"
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#include "qom/object.h"
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#include "hw/clock.h"
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#define TYPE_STM32F100_SOC "stm32f100-soc"
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OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC)
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#define STM_NUM_USARTS 3
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#define STM_NUM_SPIS 2
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#define FLASH_BASE_ADDRESS 0x08000000
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#define FLASH_SIZE (128 * 1024)
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#define SRAM_BASE_ADDRESS 0x20000000
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#define SRAM_SIZE (8 * 1024)
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struct STM32F100State {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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char *cpu_type;
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ARMv7MState armv7m;
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STM32F2XXUsartState usart[STM_NUM_USARTS];
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STM32F2XXSPIState spi[STM_NUM_SPIS];
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MemoryRegion sram;
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MemoryRegion flash;
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MemoryRegion flash_alias;
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Clock *sysclk;
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Clock *refclk;
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};
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#endif
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