Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 302b208f40373557fa11b351b5c9f43039ca8ea3.1617290165.git.alistair.francis@wdc.com
213 lines
6.4 KiB
C
213 lines
6.4 KiB
C
/*
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* RISC-V GDB Server Stub
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "exec/gdbstub.h"
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#include "cpu.h"
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int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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if (n < 32) {
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return gdb_get_regl(mem_buf, env->gpr[n]);
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} else if (n == 32) {
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return gdb_get_regl(mem_buf, env->pc);
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}
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return 0;
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}
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int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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if (n == 0) {
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/* discard writes to x0 */
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return sizeof(target_ulong);
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} else if (n < 32) {
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env->gpr[n] = ldtul_p(mem_buf);
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return sizeof(target_ulong);
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} else if (n == 32) {
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env->pc = ldtul_p(mem_buf);
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return sizeof(target_ulong);
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}
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return 0;
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}
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static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
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{
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if (n < 32) {
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if (env->misa & RVD) {
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return gdb_get_reg64(buf, env->fpr[n]);
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}
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if (env->misa & RVF) {
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return gdb_get_reg32(buf, env->fpr[n]);
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}
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/* there is hole between ft11 and fflags in fpu.xml */
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} else if (n < 36 && n > 32) {
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target_ulong val = 0;
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int result;
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/*
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* CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP
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* register 33, so we recalculate the map index.
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* This also works for CSR_FRM and CSR_FCSR.
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*/
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result = riscv_csrrw_debug(env, n - 32, &val,
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0, 0);
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if (result == RISCV_EXCP_NONE) {
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return gdb_get_regl(buf, val);
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}
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}
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return 0;
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}
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static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
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{
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if (n < 32) {
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env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
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return sizeof(uint64_t);
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/* there is hole between ft11 and fflags in fpu.xml */
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} else if (n < 36 && n > 32) {
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target_ulong val = ldtul_p(mem_buf);
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int result;
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/*
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* CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP
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* register 33, so we recalculate the map index.
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* This also works for CSR_FRM and CSR_FCSR.
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*/
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result = riscv_csrrw_debug(env, n - 32, NULL,
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val, -1);
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if (result == RISCV_EXCP_NONE) {
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return sizeof(target_ulong);
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}
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}
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return 0;
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}
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static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)
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{
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if (n < CSR_TABLE_SIZE) {
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target_ulong val = 0;
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int result;
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result = riscv_csrrw_debug(env, n, &val, 0, 0);
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if (result == RISCV_EXCP_NONE) {
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return gdb_get_regl(buf, val);
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}
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}
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return 0;
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}
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static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
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{
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if (n < CSR_TABLE_SIZE) {
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target_ulong val = ldtul_p(mem_buf);
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int result;
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result = riscv_csrrw_debug(env, n, NULL, val, -1);
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if (result == RISCV_EXCP_NONE) {
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return sizeof(target_ulong);
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}
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}
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return 0;
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}
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static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n)
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{
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if (n == 0) {
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#ifdef CONFIG_USER_ONLY
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return gdb_get_regl(buf, 0);
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#else
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return gdb_get_regl(buf, cs->priv);
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#endif
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}
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return 0;
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}
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static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
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{
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if (n == 0) {
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#ifndef CONFIG_USER_ONLY
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cs->priv = ldtul_p(mem_buf) & 0x3;
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if (cs->priv == PRV_H) {
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cs->priv = PRV_S;
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}
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#endif
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return sizeof(target_ulong);
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}
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return 0;
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}
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static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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GString *s = g_string_new(NULL);
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riscv_csr_predicate_fn predicate;
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int bitsize = riscv_cpu_is_32bit(env) ? 32 : 64;
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int i;
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g_string_printf(s, "<?xml version=\"1.0\"?>");
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g_string_append_printf(s, "<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">");
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g_string_append_printf(s, "<feature name=\"org.gnu.gdb.riscv.csr\">");
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for (i = 0; i < CSR_TABLE_SIZE; i++) {
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predicate = csr_ops[i].predicate;
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if (predicate && !predicate(env, i)) {
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if (csr_ops[i].name) {
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g_string_append_printf(s, "<reg name=\"%s\"", csr_ops[i].name);
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} else {
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g_string_append_printf(s, "<reg name=\"csr%03x\"", i);
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}
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g_string_append_printf(s, " bitsize=\"%d\"", bitsize);
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g_string_append_printf(s, " regnum=\"%d\"/>", base_reg + i);
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}
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}
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g_string_append_printf(s, "</feature>");
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cpu->dyn_csr_xml = g_string_free(s, false);
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return CSR_TABLE_SIZE;
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}
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void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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if (env->misa & RVD) {
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gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
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36, "riscv-64bit-fpu.xml", 0);
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} else if (env->misa & RVF) {
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gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
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36, "riscv-32bit-fpu.xml", 0);
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}
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#if defined(TARGET_RISCV32)
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gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
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1, "riscv-32bit-virtual.xml", 0);
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#elif defined(TARGET_RISCV64)
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gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
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1, "riscv-64bit-virtual.xml", 0);
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#endif
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gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
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riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs),
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"riscv-csr.xml", 0);
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}
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