The ARM A64 decoder's worst case number of TCG ops per instruction is 266 (for insn 0x4c800000, a post-indexed ST4 multiple-structures store). Raise the MAX_OP_PER_INSTR define accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-17-git-send-email-peter.maydell@linaro.org |
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user | ||
address-spaces.h | ||
cpu-all.h | ||
cpu-common.h | ||
cpu-defs.h | ||
cputlb.h | ||
def-helper.h | ||
exec-all.h | ||
gdbstub.h | ||
gen-icount.h | ||
hwaddr.h | ||
ioport.h | ||
memory-internal.h | ||
memory.h | ||
poison.h | ||
ram_addr.h | ||
softmmu-semi.h | ||
softmmu_exec.h | ||
softmmu_header.h | ||
softmmu_template.h | ||
spinlock.h |