9ae1329ee2
This is a model of the PCIe Host Bridge (PHB3) found on a POWER8 processor. It includes the PowerBus logic interface (PBCQ), IOMMU support, a single PCIe Gen.3 Root Complex, and support for MSI and LSI interrupt sources as found on a POWER8 system using the XICS interrupt controller. The POWER8 processor comes in different flavors: Venice, Murano, Naple, each having a different number of PHBs. To make things simpler, the models provides 3 PHB3 per chip. Some platforms, like the Firestone, can also couple PHBs on the first chip to provide more bandwidth but this is too specific to model in QEMU. XICS requires some adjustment to support the PHB3 MSI. The changes are provided here but they could be decoupled in prereq patches. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200127144506.11132-3-clg@kaod.org> [dwg: Use device_class_set_props()] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
348 lines
11 KiB
C
348 lines
11 KiB
C
/*
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* QEMU PowerPC PowerNV various definitions
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*
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* Copyright (c) 2014-2016 BenH, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef PPC_PNV_H
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#define PPC_PNV_H
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#include "hw/boards.h"
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#include "hw/sysbus.h"
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#include "hw/ipmi/ipmi.h"
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#include "hw/ppc/pnv_lpc.h"
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#include "hw/ppc/pnv_pnor.h"
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#include "hw/ppc/pnv_psi.h"
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#include "hw/ppc/pnv_occ.h"
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#include "hw/ppc/pnv_homer.h"
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#include "hw/ppc/pnv_xive.h"
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#include "hw/ppc/pnv_core.h"
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#include "hw/pci-host/pnv_phb3.h"
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#include "hw/pci-host/pnv_phb4.h"
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#define TYPE_PNV_CHIP "pnv-chip"
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#define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
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#define PNV_CHIP_CLASS(klass) \
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OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP)
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#define PNV_CHIP_GET_CLASS(obj) \
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OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP)
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typedef struct PnvChip {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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uint32_t chip_id;
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uint64_t ram_start;
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uint64_t ram_size;
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uint32_t nr_cores;
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uint32_t nr_threads;
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uint64_t cores_mask;
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PnvCore **cores;
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uint32_t num_phbs;
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MemoryRegion xscom_mmio;
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MemoryRegion xscom;
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AddressSpace xscom_as;
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gchar *dt_isa_nodename;
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} PnvChip;
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#define TYPE_PNV8_CHIP "pnv8-chip"
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#define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP)
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typedef struct Pnv8Chip {
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/*< private >*/
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PnvChip parent_obj;
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/*< public >*/
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MemoryRegion icp_mmio;
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PnvLpcController lpc;
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Pnv8Psi psi;
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PnvOCC occ;
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PnvHomer homer;
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#define PNV8_CHIP_PHB3_MAX 4
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PnvPHB3 phbs[PNV8_CHIP_PHB3_MAX];
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XICSFabric *xics;
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} Pnv8Chip;
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#define TYPE_PNV9_CHIP "pnv9-chip"
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#define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP)
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typedef struct Pnv9Chip {
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/*< private >*/
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PnvChip parent_obj;
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/*< public >*/
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PnvXive xive;
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Pnv9Psi psi;
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PnvLpcController lpc;
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PnvOCC occ;
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PnvHomer homer;
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uint32_t nr_quads;
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PnvQuad *quads;
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#define PNV9_CHIP_MAX_PEC 3
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PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC];
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} Pnv9Chip;
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/*
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* A SMT8 fused core is a pair of SMT4 cores.
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*/
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#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
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#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
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#define TYPE_PNV10_CHIP "pnv10-chip"
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#define PNV10_CHIP(obj) OBJECT_CHECK(Pnv10Chip, (obj), TYPE_PNV10_CHIP)
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typedef struct Pnv10Chip {
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/*< private >*/
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PnvChip parent_obj;
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/*< public >*/
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Pnv9Psi psi;
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PnvLpcController lpc;
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} Pnv10Chip;
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typedef struct PnvChipClass {
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/*< private >*/
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SysBusDeviceClass parent_class;
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/*< public >*/
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uint64_t chip_cfam_id;
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uint64_t cores_mask;
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uint32_t num_phbs;
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DeviceRealize parent_realize;
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uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
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void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
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void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
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void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
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void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon);
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ISABus *(*isa_create)(PnvChip *chip, Error **errp);
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void (*dt_populate)(PnvChip *chip, void *fdt);
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void (*pic_print_info)(PnvChip *chip, Monitor *mon);
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uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id);
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uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr);
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} PnvChipClass;
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#define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
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#define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
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#define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
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#define PNV_CHIP_POWER8E(obj) \
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OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E)
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#define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
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#define PNV_CHIP_POWER8(obj) \
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OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8)
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#define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
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#define PNV_CHIP_POWER8NVL(obj) \
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OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL)
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#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0")
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#define PNV_CHIP_POWER9(obj) \
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OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9)
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#define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v1.0")
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#define PNV_CHIP_POWER10(obj) \
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OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER10)
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/*
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* This generates a HW chip id depending on an index, as found on a
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* two socket system with dual chip modules :
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*
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* 0x0, 0x1, 0x10, 0x11
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*
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* 4 chips should be the maximum
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*
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* TODO: use a machine property to define the chip ids
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*/
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#define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1))
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/*
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* Converts back a HW chip id to an index. This is useful to calculate
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* the MMIO addresses of some controllers which depend on the chip id.
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*/
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#define PNV_CHIP_INDEX(chip) \
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(((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
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PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
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#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
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#define PNV_MACHINE(obj) \
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OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE)
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#define PNV_MACHINE_GET_CLASS(obj) \
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OBJECT_GET_CLASS(PnvMachineClass, obj, TYPE_PNV_MACHINE)
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#define PNV_MACHINE_CLASS(klass) \
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OBJECT_CLASS_CHECK(PnvMachineClass, klass, TYPE_PNV_MACHINE)
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typedef struct PnvMachineState PnvMachineState;
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typedef struct PnvMachineClass {
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/*< private >*/
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MachineClass parent_class;
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/*< public >*/
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const char *compat;
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int compat_size;
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void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt);
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} PnvMachineClass;
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struct PnvMachineState {
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/*< private >*/
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MachineState parent_obj;
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uint32_t initrd_base;
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long initrd_size;
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uint32_t num_chips;
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PnvChip **chips;
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ISABus *isa_bus;
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uint32_t cpld_irqstate;
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IPMIBmc *bmc;
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Notifier powerdown_notifier;
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PnvPnor *pnor;
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hwaddr fw_load_addr;
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};
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#define PNV_FDT_ADDR 0x01000000
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#define PNV_TIMEBASE_FREQ 512000000ULL
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/*
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* BMC helpers
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*/
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void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
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void pnv_bmc_powerdown(IPMIBmc *bmc);
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IPMIBmc *pnv_bmc_create(PnvPnor *pnor);
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/*
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* POWER8 MMIO base addresses
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*/
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#define PNV_XSCOM_SIZE 0x800000000ull
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#define PNV_XSCOM_BASE(chip) \
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(0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
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#define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
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#define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull
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#define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \
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PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip)))
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#define PNV_HOMER_SIZE 0x0000000000400000ull
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#define PNV_HOMER_BASE(chip) \
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(0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE)
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/*
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* XSCOM 0x20109CA defines the ICP BAR:
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*
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* 0:29 : bits 14 to 43 of address to define 1 MB region.
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* 30 : 1 to enable ICP to receive loads/stores against its BAR region
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* 31:63 : Constant 0
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*
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* Usually defined as :
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*
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* 0xffffe00200000000 -> 0x0003ffff80000000
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* 0xffffe00600000000 -> 0x0003ffff80100000
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* 0xffffe02200000000 -> 0x0003ffff80800000
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* 0xffffe02600000000 -> 0x0003ffff80900000
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*/
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#define PNV_ICP_SIZE 0x0000000000100000ull
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#define PNV_ICP_BASE(chip) \
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(0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE)
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#define PNV_PSIHB_SIZE 0x0000000000100000ull
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#define PNV_PSIHB_BASE(chip) \
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(0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE)
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#define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull
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#define PNV_PSIHB_FSP_BASE(chip) \
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(0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \
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PNV_PSIHB_FSP_SIZE)
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/*
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* POWER9 MMIO base addresses
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*/
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#define PNV9_CHIP_BASE(chip, base) \
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((base) + ((uint64_t) (chip)->chip_id << 42))
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#define PNV9_XIVE_VC_SIZE 0x0000008000000000ull
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#define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull)
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#define PNV9_XIVE_PC_SIZE 0x0000001000000000ull
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#define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull)
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#define PNV9_LPCM_SIZE 0x0000000100000000ull
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#define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull)
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#define PNV9_PSIHB_SIZE 0x0000000000100000ull
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#define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull)
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#define PNV9_XIVE_IC_SIZE 0x0000000000080000ull
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#define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull)
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#define PNV9_XIVE_TM_SIZE 0x0000000000040000ull
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#define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull)
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#define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull
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#define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull)
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#define PNV9_XSCOM_SIZE 0x0000000400000000ull
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#define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull)
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#define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
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#define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull
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#define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \
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PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip)))
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#define PNV9_HOMER_SIZE 0x0000000000400000ull
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#define PNV9_HOMER_BASE(chip) \
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(0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE)
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/*
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* POWER10 MMIO base addresses - 16TB stride per chip
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*/
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#define PNV10_CHIP_BASE(chip, base) \
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((base) + ((uint64_t) (chip)->chip_id << 44))
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#define PNV10_XSCOM_SIZE 0x0000000400000000ull
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#define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull)
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#define PNV10_LPCM_SIZE 0x0000000100000000ull
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#define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull)
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#define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull
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#define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull)
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#define PNV10_PSIHB_SIZE 0x0000000000100000ull
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#define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull)
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#endif /* PPC_PNV_H */
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