The GICv2 introduces a new CPU interface register GICC_DIR, which allows an OS to split the "priority drop" and "deactivate interrupt" parts of interrupt completion. Implement this register. (Note that the register is at offset 0x1000 in the CPU interface, which means it is on a different 4K page from all the other registers.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1456854176-7813-1-git-send-email-peter.maydell@linaro.org
290 lines
9.4 KiB
C
290 lines
9.4 KiB
C
/*
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* ARM GIC support - common bits of emulated and KVM kernel model
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*
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* Copyright (c) 2012 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "gic_internal.h"
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#include "hw/arm/linux-boot-if.h"
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static void gic_pre_save(void *opaque)
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{
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GICState *s = (GICState *)opaque;
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ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
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if (c->pre_save) {
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c->pre_save(s);
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}
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}
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static int gic_post_load(void *opaque, int version_id)
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{
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GICState *s = (GICState *)opaque;
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ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
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if (c->post_load) {
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c->post_load(s);
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}
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return 0;
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}
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static const VMStateDescription vmstate_gic_irq_state = {
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.name = "arm_gic_irq_state",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(enabled, gic_irq_state),
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VMSTATE_UINT8(pending, gic_irq_state),
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VMSTATE_UINT8(active, gic_irq_state),
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VMSTATE_UINT8(level, gic_irq_state),
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VMSTATE_BOOL(model, gic_irq_state),
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VMSTATE_BOOL(edge_trigger, gic_irq_state),
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VMSTATE_UINT8(group, gic_irq_state),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_gic = {
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.name = "arm_gic",
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.version_id = 12,
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.minimum_version_id = 12,
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.pre_save = gic_pre_save,
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.post_load = gic_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(ctlr, GICState),
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VMSTATE_UINT32_ARRAY(cpu_ctlr, GICState, GIC_NCPU),
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VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1,
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vmstate_gic_irq_state, gic_irq_state),
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VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ),
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VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU),
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VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL),
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VMSTATE_UINT8_2DARRAY(sgi_pending, GICState, GIC_NR_SGIS, GIC_NCPU),
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VMSTATE_UINT16_ARRAY(priority_mask, GICState, GIC_NCPU),
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VMSTATE_UINT16_ARRAY(running_priority, GICState, GIC_NCPU),
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VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU),
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VMSTATE_UINT8_ARRAY(bpr, GICState, GIC_NCPU),
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VMSTATE_UINT8_ARRAY(abpr, GICState, GIC_NCPU),
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VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU),
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VMSTATE_UINT32_2DARRAY(nsapr, GICState, GIC_NR_APRS, GIC_NCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
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const MemoryRegionOps *ops)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(s);
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int i = s->num_irq - GIC_INTERNAL;
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/* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
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* GPIO array layout is thus:
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* [0..N-1] SPIs
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* [N..N+31] PPIs for CPU 0
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* [N+32..N+63] PPIs for CPU 1
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* ...
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*/
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if (s->revision != REV_NVIC) {
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i += (GIC_INTERNAL * s->num_cpu);
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}
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qdev_init_gpio_in(DEVICE(s), handler, i);
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for (i = 0; i < s->num_cpu; i++) {
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sysbus_init_irq(sbd, &s->parent_irq[i]);
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}
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for (i = 0; i < s->num_cpu; i++) {
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sysbus_init_irq(sbd, &s->parent_fiq[i]);
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}
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/* Distributor */
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memory_region_init_io(&s->iomem, OBJECT(s), ops, s, "gic_dist", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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if (s->revision != REV_NVIC) {
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/* This is the main CPU interface "for this core". It is always
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* present because it is required by both software emulation and KVM.
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* NVIC is not handled here because its CPU interface is different,
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* neither it can use KVM.
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*/
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memory_region_init_io(&s->cpuiomem[0], OBJECT(s), ops ? &ops[1] : NULL,
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s, "gic_cpu", s->revision == 2 ? 0x2000 : 0x100);
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sysbus_init_mmio(sbd, &s->cpuiomem[0]);
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}
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}
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static void arm_gic_common_realize(DeviceState *dev, Error **errp)
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{
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GICState *s = ARM_GIC_COMMON(dev);
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int num_irq = s->num_irq;
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if (s->num_cpu > GIC_NCPU) {
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error_setg(errp, "requested %u CPUs exceeds GIC maximum %d",
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s->num_cpu, GIC_NCPU);
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return;
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}
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s->num_irq += GIC_BASE_IRQ;
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if (s->num_irq > GIC_MAXIRQ) {
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error_setg(errp,
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"requested %u interrupt lines exceeds GIC maximum %d",
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num_irq, GIC_MAXIRQ);
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return;
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}
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/* ITLinesNumber is represented as (N / 32) - 1 (see
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* gic_dist_readb) so this is an implementation imposed
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* restriction, not an architectural one:
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*/
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if (s->num_irq < 32 || (s->num_irq % 32)) {
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error_setg(errp,
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"%d interrupt lines unsupported: not divisible by 32",
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num_irq);
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return;
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}
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if (s->security_extn &&
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(s->revision == REV_11MPCORE || s->revision == REV_NVIC)) {
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error_setg(errp, "this GIC revision does not implement "
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"the security extensions");
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return;
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}
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}
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static void arm_gic_common_reset(DeviceState *dev)
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{
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GICState *s = ARM_GIC_COMMON(dev);
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int i, j;
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int resetprio;
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/* If we're resetting a TZ-aware GIC as if secure firmware
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* had set it up ready to start a kernel in non-secure,
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* we need to set interrupt priorities to a "zero for the
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* NS view" value. This is particularly critical for the
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* priority_mask[] values, because if they are zero then NS
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* code cannot ever rewrite the priority to anything else.
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*/
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if (s->security_extn && s->irq_reset_nonsecure) {
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resetprio = 0x80;
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} else {
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resetprio = 0;
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}
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memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
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for (i = 0 ; i < s->num_cpu; i++) {
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if (s->revision == REV_11MPCORE) {
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s->priority_mask[i] = 0xf0;
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} else {
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s->priority_mask[i] = resetprio;
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}
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s->current_pending[i] = 1023;
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s->running_priority[i] = 0x100;
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s->cpu_ctlr[i] = 0;
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s->bpr[i] = GIC_MIN_BPR;
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s->abpr[i] = GIC_MIN_ABPR;
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for (j = 0; j < GIC_INTERNAL; j++) {
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s->priority1[j][i] = resetprio;
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}
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for (j = 0; j < GIC_NR_SGIS; j++) {
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s->sgi_pending[j][i] = 0;
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}
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}
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for (i = 0; i < GIC_NR_SGIS; i++) {
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GIC_SET_ENABLED(i, ALL_CPU_MASK);
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GIC_SET_EDGE_TRIGGER(i);
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}
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for (i = 0; i < ARRAY_SIZE(s->priority2); i++) {
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s->priority2[i] = resetprio;
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}
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for (i = 0; i < GIC_MAXIRQ; i++) {
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/* For uniprocessor GICs all interrupts always target the sole CPU */
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if (s->num_cpu == 1) {
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s->irq_target[i] = 1;
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} else {
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s->irq_target[i] = 0;
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}
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}
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if (s->security_extn && s->irq_reset_nonsecure) {
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for (i = 0; i < GIC_MAXIRQ; i++) {
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GIC_SET_GROUP(i, ALL_CPU_MASK);
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}
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}
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s->ctlr = 0;
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}
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static void arm_gic_common_linux_init(ARMLinuxBootIf *obj,
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bool secure_boot)
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{
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GICState *s = ARM_GIC_COMMON(obj);
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if (s->security_extn && !secure_boot) {
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/* We're directly booting a kernel into NonSecure. If this GIC
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* implements the security extensions then we must configure it
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* to have all the interrupts be NonSecure (this is a job that
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* is done by the Secure boot firmware in real hardware, and in
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* this mode QEMU is acting as a minimalist firmware-and-bootloader
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* equivalent).
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*/
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s->irq_reset_nonsecure = true;
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}
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}
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static Property arm_gic_common_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1),
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DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32),
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/* Revision can be 1 or 2 for GIC architecture specification
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* versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC.
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* (Internally, 0xffffffff also indicates "not a GIC but an NVIC".)
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*/
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DEFINE_PROP_UINT32("revision", GICState, revision, 1),
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/* True if the GIC should implement the security extensions */
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DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void arm_gic_common_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
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dc->reset = arm_gic_common_reset;
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dc->realize = arm_gic_common_realize;
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dc->props = arm_gic_common_properties;
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dc->vmsd = &vmstate_gic;
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albifc->arm_linux_init = arm_gic_common_linux_init;
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}
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static const TypeInfo arm_gic_common_type = {
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.name = TYPE_ARM_GIC_COMMON,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(GICState),
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.class_size = sizeof(ARMGICCommonClass),
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.class_init = arm_gic_common_class_init,
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.abstract = true,
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.interfaces = (InterfaceInfo []) {
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{ TYPE_ARM_LINUX_BOOT_IF },
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{ },
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},
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};
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static void register_types(void)
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{
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type_register_static(&arm_gic_common_type);
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}
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type_init(register_types)
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