Added the hmp command to query io apic state, may be usefull after guest crashes to understand IRQ routing in guest. Implementation is only for kvm here. The dump will look like (qemu) info ioapic ioapic id=0x00 sel=0x26 (redir[11]) pin 0 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical pin 1 0x0000000000000031 dest=0 vec=49 active-hi edge fixed physical ... pin 23 0x0000000000010000 dest=0 vec=0 active-hi edge masked fixed physical IRR (none) Remote IRR (none) Signed-off-by: Pavel Butsykin <pbutsykin@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Andreas Färber <afaerber@suse.de> Message-Id: <1442927901-1084-9-git-send-email-den@openvz.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
179 lines
4.4 KiB
C
179 lines
4.4 KiB
C
/*
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* KVM in-kernel IOPIC support
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*
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* Copyright (c) 2011 Siemens AG
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*
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* Authors:
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* Jan Kiszka <jan.kiszka@siemens.com>
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*
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* This work is licensed under the terms of the GNU GPL version 2.
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* See the COPYING file in the top-level directory.
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*/
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#include "monitor/monitor.h"
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#include "hw/i386/pc.h"
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#include "hw/i386/ioapic_internal.h"
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#include "hw/i386/apic_internal.h"
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#include "sysemu/kvm.h"
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/* PC Utility function */
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void kvm_pc_setup_irq_routing(bool pci_enabled)
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{
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KVMState *s = kvm_state;
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int i;
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if (kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
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for (i = 0; i < 8; ++i) {
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if (i == 2) {
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continue;
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}
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_MASTER, i);
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}
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for (i = 8; i < 16; ++i) {
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
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}
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if (pci_enabled) {
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for (i = 0; i < 24; ++i) {
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if (i == 0) {
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, 2);
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} else if (i != 2) {
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, i);
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}
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}
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}
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kvm_irqchip_commit_routes(s);
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}
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}
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void kvm_pc_gsi_handler(void *opaque, int n, int level)
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{
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GSIState *s = opaque;
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if (n < ISA_NUM_IRQS) {
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/* Kernel will forward to both PIC and IOAPIC */
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qemu_set_irq(s->i8259_irq[n], level);
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} else {
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qemu_set_irq(s->ioapic_irq[n], level);
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}
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}
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typedef struct KVMIOAPICState KVMIOAPICState;
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struct KVMIOAPICState {
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IOAPICCommonState ioapic;
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uint32_t kvm_gsi_base;
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};
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static void kvm_ioapic_get(IOAPICCommonState *s)
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{
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struct kvm_irqchip chip;
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struct kvm_ioapic_state *kioapic;
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int ret, i;
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chip.chip_id = KVM_IRQCHIP_IOAPIC;
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ret = kvm_vm_ioctl(kvm_state, KVM_GET_IRQCHIP, &chip);
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if (ret < 0) {
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fprintf(stderr, "KVM_GET_IRQCHIP failed: %s\n", strerror(ret));
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abort();
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}
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kioapic = &chip.chip.ioapic;
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s->id = kioapic->id;
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s->ioregsel = kioapic->ioregsel;
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s->irr = kioapic->irr;
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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s->ioredtbl[i] = kioapic->redirtbl[i].bits;
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}
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}
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static void kvm_ioapic_put(IOAPICCommonState *s)
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{
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struct kvm_irqchip chip;
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struct kvm_ioapic_state *kioapic;
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int ret, i;
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chip.chip_id = KVM_IRQCHIP_IOAPIC;
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kioapic = &chip.chip.ioapic;
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kioapic->id = s->id;
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kioapic->ioregsel = s->ioregsel;
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kioapic->base_address = s->busdev.mmio[0].addr;
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kioapic->irr = s->irr;
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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kioapic->redirtbl[i].bits = s->ioredtbl[i];
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}
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ret = kvm_vm_ioctl(kvm_state, KVM_SET_IRQCHIP, &chip);
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if (ret < 0) {
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fprintf(stderr, "KVM_GET_IRQCHIP failed: %s\n", strerror(ret));
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abort();
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}
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}
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void kvm_ioapic_dump_state(Monitor *mon, const QDict *qdict)
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{
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IOAPICCommonState s;
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kvm_ioapic_get(&s);
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ioapic_print_redtbl(mon, &s);
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}
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static void kvm_ioapic_reset(DeviceState *dev)
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{
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IOAPICCommonState *s = IOAPIC_COMMON(dev);
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ioapic_reset_common(dev);
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kvm_ioapic_put(s);
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}
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static void kvm_ioapic_set_irq(void *opaque, int irq, int level)
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{
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KVMIOAPICState *s = opaque;
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int delivered;
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delivered = kvm_set_irq(kvm_state, s->kvm_gsi_base + irq, level);
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apic_report_irq_delivered(delivered);
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}
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static void kvm_ioapic_realize(DeviceState *dev, Error **errp)
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{
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IOAPICCommonState *s = IOAPIC_COMMON(dev);
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memory_region_init_reservation(&s->io_memory, NULL, "kvm-ioapic", 0x1000);
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qdev_init_gpio_in(dev, kvm_ioapic_set_irq, IOAPIC_NUM_PINS);
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}
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static Property kvm_ioapic_properties[] = {
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DEFINE_PROP_UINT32("gsi_base", KVMIOAPICState, kvm_gsi_base, 0),
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DEFINE_PROP_END_OF_LIST()
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};
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static void kvm_ioapic_class_init(ObjectClass *klass, void *data)
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{
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IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->realize = kvm_ioapic_realize;
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k->pre_save = kvm_ioapic_get;
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k->post_load = kvm_ioapic_put;
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dc->reset = kvm_ioapic_reset;
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dc->props = kvm_ioapic_properties;
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}
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static const TypeInfo kvm_ioapic_info = {
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.name = "kvm-ioapic",
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.parent = TYPE_IOAPIC_COMMON,
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.instance_size = sizeof(KVMIOAPICState),
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.class_init = kvm_ioapic_class_init,
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};
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static void kvm_ioapic_register_types(void)
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{
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type_register_static(&kvm_ioapic_info);
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}
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type_init(kvm_ioapic_register_types)
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