Compress two lines into a single line if immediate return statement is found. It also remove variables progress, val, data, ret and sock as they are no longer needed. Remove space between function "mixer_load" and '(' to fix the checkpatch.pl error:- ERROR: space prohibited between function name and open parenthesis '(' Done using following coccinelle script: @@ local idexpression ret; expression e; @@ -ret = +return e; -return ret; Signed-off-by: Simran Singhal <singhalsimran0@gmail.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20200401165314.GA3213@simran-Inspiron-5558> [lv: in handle_aiocb_write_zeroes_unmap() move "int ret" inside the #ifdef] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
1372 lines
38 KiB
C
1372 lines
38 KiB
C
/*
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* NVMe block driver based on vfio
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*
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* Copyright 2016 - 2018 Red Hat, Inc.
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*
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* Authors:
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* Fam Zheng <famz@redhat.com>
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* Paolo Bonzini <pbonzini@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include <linux/vfio.h>
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#include "qapi/error.h"
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#include "qapi/qmp/qdict.h"
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#include "qapi/qmp/qstring.h"
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#include "qemu/error-report.h"
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#include "qemu/main-loop.h"
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#include "qemu/module.h"
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#include "qemu/cutils.h"
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#include "qemu/option.h"
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#include "qemu/vfio-helpers.h"
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#include "block/block_int.h"
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#include "sysemu/replay.h"
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#include "trace.h"
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#include "block/nvme.h"
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#define NVME_SQ_ENTRY_BYTES 64
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#define NVME_CQ_ENTRY_BYTES 16
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#define NVME_QUEUE_SIZE 128
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#define NVME_BAR_SIZE 8192
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typedef struct {
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int32_t head, tail;
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uint8_t *queue;
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uint64_t iova;
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/* Hardware MMIO register */
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volatile uint32_t *doorbell;
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} NVMeQueue;
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typedef struct {
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BlockCompletionFunc *cb;
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void *opaque;
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int cid;
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void *prp_list_page;
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uint64_t prp_list_iova;
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bool busy;
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} NVMeRequest;
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typedef struct {
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CoQueue free_req_queue;
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QemuMutex lock;
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/* Fields protected by BQL */
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int index;
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uint8_t *prp_list_pages;
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/* Fields protected by @lock */
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NVMeQueue sq, cq;
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int cq_phase;
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NVMeRequest reqs[NVME_QUEUE_SIZE];
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bool busy;
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int need_kick;
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int inflight;
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} NVMeQueuePair;
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/* Memory mapped registers */
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typedef volatile struct {
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uint64_t cap;
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uint32_t vs;
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uint32_t intms;
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uint32_t intmc;
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uint32_t cc;
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uint32_t reserved0;
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uint32_t csts;
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uint32_t nssr;
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uint32_t aqa;
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uint64_t asq;
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uint64_t acq;
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uint32_t cmbloc;
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uint32_t cmbsz;
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uint8_t reserved1[0xec0];
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uint8_t cmd_set_specfic[0x100];
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uint32_t doorbells[];
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} NVMeRegs;
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QEMU_BUILD_BUG_ON(offsetof(NVMeRegs, doorbells) != 0x1000);
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typedef struct {
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AioContext *aio_context;
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QEMUVFIOState *vfio;
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NVMeRegs *regs;
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/* The submission/completion queue pairs.
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* [0]: admin queue.
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* [1..]: io queues.
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*/
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NVMeQueuePair **queues;
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int nr_queues;
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size_t page_size;
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/* How many uint32_t elements does each doorbell entry take. */
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size_t doorbell_scale;
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bool write_cache_supported;
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EventNotifier irq_notifier;
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uint64_t nsze; /* Namespace size reported by identify command */
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int nsid; /* The namespace id to read/write data. */
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int blkshift;
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uint64_t max_transfer;
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bool plugged;
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bool supports_write_zeroes;
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bool supports_discard;
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CoMutex dma_map_lock;
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CoQueue dma_flush_queue;
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/* Total size of mapped qiov, accessed under dma_map_lock */
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int dma_map_count;
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/* PCI address (required for nvme_refresh_filename()) */
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char *device;
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} BDRVNVMeState;
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#define NVME_BLOCK_OPT_DEVICE "device"
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#define NVME_BLOCK_OPT_NAMESPACE "namespace"
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static QemuOptsList runtime_opts = {
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.name = "nvme",
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.head = QTAILQ_HEAD_INITIALIZER(runtime_opts.head),
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.desc = {
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{
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.name = NVME_BLOCK_OPT_DEVICE,
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.type = QEMU_OPT_STRING,
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.help = "NVMe PCI device address",
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},
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{
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.name = NVME_BLOCK_OPT_NAMESPACE,
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.type = QEMU_OPT_NUMBER,
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.help = "NVMe namespace",
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},
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{ /* end of list */ }
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},
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};
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static void nvme_init_queue(BlockDriverState *bs, NVMeQueue *q,
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int nentries, int entry_bytes, Error **errp)
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{
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BDRVNVMeState *s = bs->opaque;
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size_t bytes;
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int r;
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bytes = ROUND_UP(nentries * entry_bytes, s->page_size);
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q->head = q->tail = 0;
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q->queue = qemu_try_blockalign0(bs, bytes);
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if (!q->queue) {
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error_setg(errp, "Cannot allocate queue");
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return;
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}
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r = qemu_vfio_dma_map(s->vfio, q->queue, bytes, false, &q->iova);
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if (r) {
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error_setg(errp, "Cannot map queue");
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}
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}
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static void nvme_free_queue_pair(BlockDriverState *bs, NVMeQueuePair *q)
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{
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qemu_vfree(q->prp_list_pages);
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qemu_vfree(q->sq.queue);
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qemu_vfree(q->cq.queue);
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qemu_mutex_destroy(&q->lock);
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g_free(q);
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}
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static void nvme_free_req_queue_cb(void *opaque)
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{
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NVMeQueuePair *q = opaque;
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qemu_mutex_lock(&q->lock);
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while (qemu_co_enter_next(&q->free_req_queue, &q->lock)) {
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/* Retry all pending requests */
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}
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qemu_mutex_unlock(&q->lock);
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}
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static NVMeQueuePair *nvme_create_queue_pair(BlockDriverState *bs,
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int idx, int size,
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Error **errp)
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{
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int i, r;
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BDRVNVMeState *s = bs->opaque;
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Error *local_err = NULL;
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NVMeQueuePair *q = g_new0(NVMeQueuePair, 1);
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uint64_t prp_list_iova;
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qemu_mutex_init(&q->lock);
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q->index = idx;
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qemu_co_queue_init(&q->free_req_queue);
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q->prp_list_pages = qemu_blockalign0(bs, s->page_size * NVME_QUEUE_SIZE);
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r = qemu_vfio_dma_map(s->vfio, q->prp_list_pages,
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s->page_size * NVME_QUEUE_SIZE,
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false, &prp_list_iova);
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if (r) {
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goto fail;
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}
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for (i = 0; i < NVME_QUEUE_SIZE; i++) {
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NVMeRequest *req = &q->reqs[i];
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req->cid = i + 1;
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req->prp_list_page = q->prp_list_pages + i * s->page_size;
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req->prp_list_iova = prp_list_iova + i * s->page_size;
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}
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nvme_init_queue(bs, &q->sq, size, NVME_SQ_ENTRY_BYTES, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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goto fail;
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}
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q->sq.doorbell = &s->regs->doorbells[idx * 2 * s->doorbell_scale];
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nvme_init_queue(bs, &q->cq, size, NVME_CQ_ENTRY_BYTES, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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goto fail;
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}
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q->cq.doorbell = &s->regs->doorbells[(idx * 2 + 1) * s->doorbell_scale];
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return q;
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fail:
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nvme_free_queue_pair(bs, q);
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return NULL;
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}
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/* With q->lock */
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static void nvme_kick(BDRVNVMeState *s, NVMeQueuePair *q)
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{
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if (s->plugged || !q->need_kick) {
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return;
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}
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trace_nvme_kick(s, q->index);
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assert(!(q->sq.tail & 0xFF00));
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/* Fence the write to submission queue entry before notifying the device. */
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smp_wmb();
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*q->sq.doorbell = cpu_to_le32(q->sq.tail);
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q->inflight += q->need_kick;
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q->need_kick = 0;
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}
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/* Find a free request element if any, otherwise:
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* a) if in coroutine context, try to wait for one to become available;
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* b) if not in coroutine, return NULL;
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*/
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static NVMeRequest *nvme_get_free_req(NVMeQueuePair *q)
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{
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int i;
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NVMeRequest *req = NULL;
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qemu_mutex_lock(&q->lock);
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while (q->inflight + q->need_kick > NVME_QUEUE_SIZE - 2) {
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/* We have to leave one slot empty as that is the full queue case (head
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* == tail + 1). */
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if (qemu_in_coroutine()) {
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trace_nvme_free_req_queue_wait(q);
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qemu_co_queue_wait(&q->free_req_queue, &q->lock);
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} else {
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qemu_mutex_unlock(&q->lock);
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return NULL;
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}
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}
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for (i = 0; i < NVME_QUEUE_SIZE; i++) {
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if (!q->reqs[i].busy) {
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q->reqs[i].busy = true;
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req = &q->reqs[i];
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break;
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}
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}
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/* We have checked inflight and need_kick while holding q->lock, so one
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* free req must be available. */
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assert(req);
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qemu_mutex_unlock(&q->lock);
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return req;
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}
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static inline int nvme_translate_error(const NvmeCqe *c)
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{
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uint16_t status = (le16_to_cpu(c->status) >> 1) & 0xFF;
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if (status) {
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trace_nvme_error(le32_to_cpu(c->result),
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le16_to_cpu(c->sq_head),
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le16_to_cpu(c->sq_id),
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le16_to_cpu(c->cid),
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le16_to_cpu(status));
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}
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switch (status) {
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case 0:
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return 0;
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case 1:
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return -ENOSYS;
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case 2:
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return -EINVAL;
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default:
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return -EIO;
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}
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}
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|
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/* With q->lock */
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static bool nvme_process_completion(BDRVNVMeState *s, NVMeQueuePair *q)
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{
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bool progress = false;
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NVMeRequest *preq;
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NVMeRequest req;
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NvmeCqe *c;
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trace_nvme_process_completion(s, q->index, q->inflight);
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if (q->busy || s->plugged) {
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trace_nvme_process_completion_queue_busy(s, q->index);
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return false;
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}
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q->busy = true;
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assert(q->inflight >= 0);
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while (q->inflight) {
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int16_t cid;
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c = (NvmeCqe *)&q->cq.queue[q->cq.head * NVME_CQ_ENTRY_BYTES];
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if ((le16_to_cpu(c->status) & 0x1) == q->cq_phase) {
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break;
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}
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q->cq.head = (q->cq.head + 1) % NVME_QUEUE_SIZE;
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if (!q->cq.head) {
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q->cq_phase = !q->cq_phase;
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}
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cid = le16_to_cpu(c->cid);
|
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if (cid == 0 || cid > NVME_QUEUE_SIZE) {
|
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fprintf(stderr, "Unexpected CID in completion queue: %" PRIu32 "\n",
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cid);
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continue;
|
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}
|
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assert(cid <= NVME_QUEUE_SIZE);
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trace_nvme_complete_command(s, q->index, cid);
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preq = &q->reqs[cid - 1];
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req = *preq;
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assert(req.cid == cid);
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assert(req.cb);
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preq->busy = false;
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preq->cb = preq->opaque = NULL;
|
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qemu_mutex_unlock(&q->lock);
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req.cb(req.opaque, nvme_translate_error(c));
|
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qemu_mutex_lock(&q->lock);
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q->inflight--;
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progress = true;
|
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}
|
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if (progress) {
|
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/* Notify the device so it can post more completions. */
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smp_mb_release();
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*q->cq.doorbell = cpu_to_le32(q->cq.head);
|
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if (!qemu_co_queue_empty(&q->free_req_queue)) {
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replay_bh_schedule_oneshot_event(s->aio_context,
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nvme_free_req_queue_cb, q);
|
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}
|
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}
|
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q->busy = false;
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return progress;
|
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}
|
|
|
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static void nvme_trace_command(const NvmeCmd *cmd)
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{
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int i;
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|
|
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for (i = 0; i < 8; ++i) {
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uint8_t *cmdp = (uint8_t *)cmd + i * 8;
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trace_nvme_submit_command_raw(cmdp[0], cmdp[1], cmdp[2], cmdp[3],
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cmdp[4], cmdp[5], cmdp[6], cmdp[7]);
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}
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}
|
|
|
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static void nvme_submit_command(BDRVNVMeState *s, NVMeQueuePair *q,
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NVMeRequest *req,
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NvmeCmd *cmd, BlockCompletionFunc cb,
|
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void *opaque)
|
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{
|
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assert(!req->cb);
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req->cb = cb;
|
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req->opaque = opaque;
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cmd->cid = cpu_to_le32(req->cid);
|
|
|
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trace_nvme_submit_command(s, q->index, req->cid);
|
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nvme_trace_command(cmd);
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qemu_mutex_lock(&q->lock);
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memcpy((uint8_t *)q->sq.queue +
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q->sq.tail * NVME_SQ_ENTRY_BYTES, cmd, sizeof(*cmd));
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q->sq.tail = (q->sq.tail + 1) % NVME_QUEUE_SIZE;
|
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q->need_kick++;
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nvme_kick(s, q);
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nvme_process_completion(s, q);
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qemu_mutex_unlock(&q->lock);
|
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}
|
|
|
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static void nvme_cmd_sync_cb(void *opaque, int ret)
|
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{
|
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int *pret = opaque;
|
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*pret = ret;
|
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aio_wait_kick();
|
|
}
|
|
|
|
static int nvme_cmd_sync(BlockDriverState *bs, NVMeQueuePair *q,
|
|
NvmeCmd *cmd)
|
|
{
|
|
NVMeRequest *req;
|
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BDRVNVMeState *s = bs->opaque;
|
|
int ret = -EINPROGRESS;
|
|
req = nvme_get_free_req(q);
|
|
if (!req) {
|
|
return -EBUSY;
|
|
}
|
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nvme_submit_command(s, q, req, cmd, nvme_cmd_sync_cb, &ret);
|
|
|
|
BDRV_POLL_WHILE(bs, ret == -EINPROGRESS);
|
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return ret;
|
|
}
|
|
|
|
static void nvme_identify(BlockDriverState *bs, int namespace, Error **errp)
|
|
{
|
|
BDRVNVMeState *s = bs->opaque;
|
|
NvmeIdCtrl *idctrl;
|
|
NvmeIdNs *idns;
|
|
NvmeLBAF *lbaf;
|
|
uint8_t *resp;
|
|
uint16_t oncs;
|
|
int r;
|
|
uint64_t iova;
|
|
NvmeCmd cmd = {
|
|
.opcode = NVME_ADM_CMD_IDENTIFY,
|
|
.cdw10 = cpu_to_le32(0x1),
|
|
};
|
|
|
|
resp = qemu_try_blockalign0(bs, sizeof(NvmeIdCtrl));
|
|
if (!resp) {
|
|
error_setg(errp, "Cannot allocate buffer for identify response");
|
|
goto out;
|
|
}
|
|
idctrl = (NvmeIdCtrl *)resp;
|
|
idns = (NvmeIdNs *)resp;
|
|
r = qemu_vfio_dma_map(s->vfio, resp, sizeof(NvmeIdCtrl), true, &iova);
|
|
if (r) {
|
|
error_setg(errp, "Cannot map buffer for DMA");
|
|
goto out;
|
|
}
|
|
cmd.prp1 = cpu_to_le64(iova);
|
|
|
|
if (nvme_cmd_sync(bs, s->queues[0], &cmd)) {
|
|
error_setg(errp, "Failed to identify controller");
|
|
goto out;
|
|
}
|
|
|
|
if (le32_to_cpu(idctrl->nn) < namespace) {
|
|
error_setg(errp, "Invalid namespace");
|
|
goto out;
|
|
}
|
|
s->write_cache_supported = le32_to_cpu(idctrl->vwc) & 0x1;
|
|
s->max_transfer = (idctrl->mdts ? 1 << idctrl->mdts : 0) * s->page_size;
|
|
/* For now the page list buffer per command is one page, to hold at most
|
|
* s->page_size / sizeof(uint64_t) entries. */
|
|
s->max_transfer = MIN_NON_ZERO(s->max_transfer,
|
|
s->page_size / sizeof(uint64_t) * s->page_size);
|
|
|
|
oncs = le16_to_cpu(idctrl->oncs);
|
|
s->supports_write_zeroes = !!(oncs & NVME_ONCS_WRITE_ZEROS);
|
|
s->supports_discard = !!(oncs & NVME_ONCS_DSM);
|
|
|
|
memset(resp, 0, 4096);
|
|
|
|
cmd.cdw10 = 0;
|
|
cmd.nsid = cpu_to_le32(namespace);
|
|
if (nvme_cmd_sync(bs, s->queues[0], &cmd)) {
|
|
error_setg(errp, "Failed to identify namespace");
|
|
goto out;
|
|
}
|
|
|
|
s->nsze = le64_to_cpu(idns->nsze);
|
|
lbaf = &idns->lbaf[NVME_ID_NS_FLBAS_INDEX(idns->flbas)];
|
|
|
|
if (NVME_ID_NS_DLFEAT_WRITE_ZEROES(idns->dlfeat) &&
|
|
NVME_ID_NS_DLFEAT_READ_BEHAVIOR(idns->dlfeat) ==
|
|
NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES) {
|
|
bs->supported_write_flags |= BDRV_REQ_MAY_UNMAP;
|
|
}
|
|
|
|
if (lbaf->ms) {
|
|
error_setg(errp, "Namespaces with metadata are not yet supported");
|
|
goto out;
|
|
}
|
|
|
|
if (lbaf->ds < BDRV_SECTOR_BITS || lbaf->ds > 12 ||
|
|
(1 << lbaf->ds) > s->page_size)
|
|
{
|
|
error_setg(errp, "Namespace has unsupported block size (2^%d)",
|
|
lbaf->ds);
|
|
goto out;
|
|
}
|
|
|
|
s->blkshift = lbaf->ds;
|
|
out:
|
|
qemu_vfio_dma_unmap(s->vfio, resp);
|
|
qemu_vfree(resp);
|
|
}
|
|
|
|
static bool nvme_poll_queues(BDRVNVMeState *s)
|
|
{
|
|
bool progress = false;
|
|
int i;
|
|
|
|
for (i = 0; i < s->nr_queues; i++) {
|
|
NVMeQueuePair *q = s->queues[i];
|
|
qemu_mutex_lock(&q->lock);
|
|
while (nvme_process_completion(s, q)) {
|
|
/* Keep polling */
|
|
progress = true;
|
|
}
|
|
qemu_mutex_unlock(&q->lock);
|
|
}
|
|
return progress;
|
|
}
|
|
|
|
static void nvme_handle_event(EventNotifier *n)
|
|
{
|
|
BDRVNVMeState *s = container_of(n, BDRVNVMeState, irq_notifier);
|
|
|
|
trace_nvme_handle_event(s);
|
|
event_notifier_test_and_clear(n);
|
|
nvme_poll_queues(s);
|
|
}
|
|
|
|
static bool nvme_add_io_queue(BlockDriverState *bs, Error **errp)
|
|
{
|
|
BDRVNVMeState *s = bs->opaque;
|
|
int n = s->nr_queues;
|
|
NVMeQueuePair *q;
|
|
NvmeCmd cmd;
|
|
int queue_size = NVME_QUEUE_SIZE;
|
|
|
|
q = nvme_create_queue_pair(bs, n, queue_size, errp);
|
|
if (!q) {
|
|
return false;
|
|
}
|
|
cmd = (NvmeCmd) {
|
|
.opcode = NVME_ADM_CMD_CREATE_CQ,
|
|
.prp1 = cpu_to_le64(q->cq.iova),
|
|
.cdw10 = cpu_to_le32(((queue_size - 1) << 16) | (n & 0xFFFF)),
|
|
.cdw11 = cpu_to_le32(0x3),
|
|
};
|
|
if (nvme_cmd_sync(bs, s->queues[0], &cmd)) {
|
|
error_setg(errp, "Failed to create io queue [%d]", n);
|
|
nvme_free_queue_pair(bs, q);
|
|
return false;
|
|
}
|
|
cmd = (NvmeCmd) {
|
|
.opcode = NVME_ADM_CMD_CREATE_SQ,
|
|
.prp1 = cpu_to_le64(q->sq.iova),
|
|
.cdw10 = cpu_to_le32(((queue_size - 1) << 16) | (n & 0xFFFF)),
|
|
.cdw11 = cpu_to_le32(0x1 | (n << 16)),
|
|
};
|
|
if (nvme_cmd_sync(bs, s->queues[0], &cmd)) {
|
|
error_setg(errp, "Failed to create io queue [%d]", n);
|
|
nvme_free_queue_pair(bs, q);
|
|
return false;
|
|
}
|
|
s->queues = g_renew(NVMeQueuePair *, s->queues, n + 1);
|
|
s->queues[n] = q;
|
|
s->nr_queues++;
|
|
return true;
|
|
}
|
|
|
|
static bool nvme_poll_cb(void *opaque)
|
|
{
|
|
EventNotifier *e = opaque;
|
|
BDRVNVMeState *s = container_of(e, BDRVNVMeState, irq_notifier);
|
|
|
|
trace_nvme_poll_cb(s);
|
|
return nvme_poll_queues(s);
|
|
}
|
|
|
|
static int nvme_init(BlockDriverState *bs, const char *device, int namespace,
|
|
Error **errp)
|
|
{
|
|
BDRVNVMeState *s = bs->opaque;
|
|
int ret;
|
|
uint64_t cap;
|
|
uint64_t timeout_ms;
|
|
uint64_t deadline, now;
|
|
Error *local_err = NULL;
|
|
|
|
qemu_co_mutex_init(&s->dma_map_lock);
|
|
qemu_co_queue_init(&s->dma_flush_queue);
|
|
s->device = g_strdup(device);
|
|
s->nsid = namespace;
|
|
s->aio_context = bdrv_get_aio_context(bs);
|
|
ret = event_notifier_init(&s->irq_notifier, 0);
|
|
if (ret) {
|
|
error_setg(errp, "Failed to init event notifier");
|
|
return ret;
|
|
}
|
|
|
|
s->vfio = qemu_vfio_open_pci(device, errp);
|
|
if (!s->vfio) {
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
s->regs = qemu_vfio_pci_map_bar(s->vfio, 0, 0, NVME_BAR_SIZE, errp);
|
|
if (!s->regs) {
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
/* Perform initialize sequence as described in NVMe spec "7.6.1
|
|
* Initialization". */
|
|
|
|
cap = le64_to_cpu(s->regs->cap);
|
|
if (!(cap & (1ULL << 37))) {
|
|
error_setg(errp, "Device doesn't support NVMe command set");
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
s->page_size = MAX(4096, 1 << (12 + ((cap >> 48) & 0xF)));
|
|
s->doorbell_scale = (4 << (((cap >> 32) & 0xF))) / sizeof(uint32_t);
|
|
bs->bl.opt_mem_alignment = s->page_size;
|
|
timeout_ms = MIN(500 * ((cap >> 24) & 0xFF), 30000);
|
|
|
|
/* Reset device to get a clean state. */
|
|
s->regs->cc = cpu_to_le32(le32_to_cpu(s->regs->cc) & 0xFE);
|
|
/* Wait for CSTS.RDY = 0. */
|
|
deadline = qemu_clock_get_ns(QEMU_CLOCK_REALTIME) + timeout_ms * 1000000ULL;
|
|
while (le32_to_cpu(s->regs->csts) & 0x1) {
|
|
if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) {
|
|
error_setg(errp, "Timeout while waiting for device to reset (%"
|
|
PRId64 " ms)",
|
|
timeout_ms);
|
|
ret = -ETIMEDOUT;
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
/* Set up admin queue. */
|
|
s->queues = g_new(NVMeQueuePair *, 1);
|
|
s->queues[0] = nvme_create_queue_pair(bs, 0, NVME_QUEUE_SIZE, errp);
|
|
if (!s->queues[0]) {
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
s->nr_queues = 1;
|
|
QEMU_BUILD_BUG_ON(NVME_QUEUE_SIZE & 0xF000);
|
|
s->regs->aqa = cpu_to_le32((NVME_QUEUE_SIZE << 16) | NVME_QUEUE_SIZE);
|
|
s->regs->asq = cpu_to_le64(s->queues[0]->sq.iova);
|
|
s->regs->acq = cpu_to_le64(s->queues[0]->cq.iova);
|
|
|
|
/* After setting up all control registers we can enable device now. */
|
|
s->regs->cc = cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << 20) |
|
|
(ctz32(NVME_SQ_ENTRY_BYTES) << 16) |
|
|
0x1);
|
|
/* Wait for CSTS.RDY = 1. */
|
|
now = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
|
|
deadline = now + timeout_ms * 1000000;
|
|
while (!(le32_to_cpu(s->regs->csts) & 0x1)) {
|
|
if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) {
|
|
error_setg(errp, "Timeout while waiting for device to start (%"
|
|
PRId64 " ms)",
|
|
timeout_ms);
|
|
ret = -ETIMEDOUT;
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
ret = qemu_vfio_pci_init_irq(s->vfio, &s->irq_notifier,
|
|
VFIO_PCI_MSIX_IRQ_INDEX, errp);
|
|
if (ret) {
|
|
goto out;
|
|
}
|
|
aio_set_event_notifier(bdrv_get_aio_context(bs), &s->irq_notifier,
|
|
false, nvme_handle_event, nvme_poll_cb);
|
|
|
|
nvme_identify(bs, namespace, &local_err);
|
|
if (local_err) {
|
|
error_propagate(errp, local_err);
|
|
ret = -EIO;
|
|
goto out;
|
|
}
|
|
|
|
/* Set up command queues. */
|
|
if (!nvme_add_io_queue(bs, errp)) {
|
|
ret = -EIO;
|
|
}
|
|
out:
|
|
/* Cleaning up is done in nvme_file_open() upon error. */
|
|
return ret;
|
|
}
|
|
|
|
/* Parse a filename in the format of nvme://XXXX:XX:XX.X/X. Example:
|
|
*
|
|
* nvme://0000:44:00.0/1
|
|
*
|
|
* where the "nvme://" is a fixed form of the protocol prefix, the middle part
|
|
* is the PCI address, and the last part is the namespace number starting from
|
|
* 1 according to the NVMe spec. */
|
|
static void nvme_parse_filename(const char *filename, QDict *options,
|
|
Error **errp)
|
|
{
|
|
int pref = strlen("nvme://");
|
|
|
|
if (strlen(filename) > pref && !strncmp(filename, "nvme://", pref)) {
|
|
const char *tmp = filename + pref;
|
|
char *device;
|
|
const char *namespace;
|
|
unsigned long ns;
|
|
const char *slash = strchr(tmp, '/');
|
|
if (!slash) {
|
|
qdict_put_str(options, NVME_BLOCK_OPT_DEVICE, tmp);
|
|
return;
|
|
}
|
|
device = g_strndup(tmp, slash - tmp);
|
|
qdict_put_str(options, NVME_BLOCK_OPT_DEVICE, device);
|
|
g_free(device);
|
|
namespace = slash + 1;
|
|
if (*namespace && qemu_strtoul(namespace, NULL, 10, &ns)) {
|
|
error_setg(errp, "Invalid namespace '%s', positive number expected",
|
|
namespace);
|
|
return;
|
|
}
|
|
qdict_put_str(options, NVME_BLOCK_OPT_NAMESPACE,
|
|
*namespace ? namespace : "1");
|
|
}
|
|
}
|
|
|
|
static int nvme_enable_disable_write_cache(BlockDriverState *bs, bool enable,
|
|
Error **errp)
|
|
{
|
|
int ret;
|
|
BDRVNVMeState *s = bs->opaque;
|
|
NvmeCmd cmd = {
|
|
.opcode = NVME_ADM_CMD_SET_FEATURES,
|
|
.nsid = cpu_to_le32(s->nsid),
|
|
.cdw10 = cpu_to_le32(0x06),
|
|
.cdw11 = cpu_to_le32(enable ? 0x01 : 0x00),
|
|
};
|
|
|
|
ret = nvme_cmd_sync(bs, s->queues[0], &cmd);
|
|
if (ret) {
|
|
error_setg(errp, "Failed to configure NVMe write cache");
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static void nvme_close(BlockDriverState *bs)
|
|
{
|
|
int i;
|
|
BDRVNVMeState *s = bs->opaque;
|
|
|
|
for (i = 0; i < s->nr_queues; ++i) {
|
|
nvme_free_queue_pair(bs, s->queues[i]);
|
|
}
|
|
g_free(s->queues);
|
|
aio_set_event_notifier(bdrv_get_aio_context(bs), &s->irq_notifier,
|
|
false, NULL, NULL);
|
|
event_notifier_cleanup(&s->irq_notifier);
|
|
qemu_vfio_pci_unmap_bar(s->vfio, 0, (void *)s->regs, 0, NVME_BAR_SIZE);
|
|
qemu_vfio_close(s->vfio);
|
|
|
|
g_free(s->device);
|
|
}
|
|
|
|
static int nvme_file_open(BlockDriverState *bs, QDict *options, int flags,
|
|
Error **errp)
|
|
{
|
|
const char *device;
|
|
QemuOpts *opts;
|
|
int namespace;
|
|
int ret;
|
|
BDRVNVMeState *s = bs->opaque;
|
|
|
|
bs->supported_write_flags = BDRV_REQ_FUA;
|
|
|
|
opts = qemu_opts_create(&runtime_opts, NULL, 0, &error_abort);
|
|
qemu_opts_absorb_qdict(opts, options, &error_abort);
|
|
device = qemu_opt_get(opts, NVME_BLOCK_OPT_DEVICE);
|
|
if (!device) {
|
|
error_setg(errp, "'" NVME_BLOCK_OPT_DEVICE "' option is required");
|
|
qemu_opts_del(opts);
|
|
return -EINVAL;
|
|
}
|
|
|
|
namespace = qemu_opt_get_number(opts, NVME_BLOCK_OPT_NAMESPACE, 1);
|
|
ret = nvme_init(bs, device, namespace, errp);
|
|
qemu_opts_del(opts);
|
|
if (ret) {
|
|
goto fail;
|
|
}
|
|
if (flags & BDRV_O_NOCACHE) {
|
|
if (!s->write_cache_supported) {
|
|
error_setg(errp,
|
|
"NVMe controller doesn't support write cache configuration");
|
|
ret = -EINVAL;
|
|
} else {
|
|
ret = nvme_enable_disable_write_cache(bs, !(flags & BDRV_O_NOCACHE),
|
|
errp);
|
|
}
|
|
if (ret) {
|
|
goto fail;
|
|
}
|
|
}
|
|
return 0;
|
|
fail:
|
|
nvme_close(bs);
|
|
return ret;
|
|
}
|
|
|
|
static int64_t nvme_getlength(BlockDriverState *bs)
|
|
{
|
|
BDRVNVMeState *s = bs->opaque;
|
|
return s->nsze << s->blkshift;
|
|
}
|
|
|
|
static uint32_t nvme_get_blocksize(BlockDriverState *bs)
|
|
{
|
|
BDRVNVMeState *s = bs->opaque;
|
|
assert(s->blkshift >= BDRV_SECTOR_BITS && s->blkshift <= 12);
|
|
return UINT32_C(1) << s->blkshift;
|
|
}
|
|
|
|
static int nvme_probe_blocksizes(BlockDriverState *bs, BlockSizes *bsz)
|
|
{
|
|
uint32_t blocksize = nvme_get_blocksize(bs);
|
|
bsz->phys = blocksize;
|
|
bsz->log = blocksize;
|
|
return 0;
|
|
}
|
|
|
|
/* Called with s->dma_map_lock */
|
|
static coroutine_fn int nvme_cmd_unmap_qiov(BlockDriverState *bs,
|
|
QEMUIOVector *qiov)
|
|
{
|
|
int r = 0;
|
|
BDRVNVMeState *s = bs->opaque;
|
|
|
|
s->dma_map_count -= qiov->size;
|
|
if (!s->dma_map_count && !qemu_co_queue_empty(&s->dma_flush_queue)) {
|
|
r = qemu_vfio_dma_reset_temporary(s->vfio);
|
|
if (!r) {
|
|
qemu_co_queue_restart_all(&s->dma_flush_queue);
|
|
}
|
|
}
|
|
return r;
|
|
}
|
|
|
|
/* Called with s->dma_map_lock */
|
|
static coroutine_fn int nvme_cmd_map_qiov(BlockDriverState *bs, NvmeCmd *cmd,
|
|
NVMeRequest *req, QEMUIOVector *qiov)
|
|
{
|
|
BDRVNVMeState *s = bs->opaque;
|
|
uint64_t *pagelist = req->prp_list_page;
|
|
int i, j, r;
|
|
int entries = 0;
|
|
|
|
assert(qiov->size);
|
|
assert(QEMU_IS_ALIGNED(qiov->size, s->page_size));
|
|
assert(qiov->size / s->page_size <= s->page_size / sizeof(uint64_t));
|
|
for (i = 0; i < qiov->niov; ++i) {
|
|
bool retry = true;
|
|
uint64_t iova;
|
|
try_map:
|
|
r = qemu_vfio_dma_map(s->vfio,
|
|
qiov->iov[i].iov_base,
|
|
qiov->iov[i].iov_len,
|
|
true, &iova);
|
|
if (r == -ENOMEM && retry) {
|
|
retry = false;
|
|
trace_nvme_dma_flush_queue_wait(s);
|
|
if (s->dma_map_count) {
|
|
trace_nvme_dma_map_flush(s);
|
|
qemu_co_queue_wait(&s->dma_flush_queue, &s->dma_map_lock);
|
|
} else {
|
|
r = qemu_vfio_dma_reset_temporary(s->vfio);
|
|
if (r) {
|
|
goto fail;
|
|
}
|
|
}
|
|
goto try_map;
|
|
}
|
|
if (r) {
|
|
goto fail;
|
|
}
|
|
|
|
for (j = 0; j < qiov->iov[i].iov_len / s->page_size; j++) {
|
|
pagelist[entries++] = cpu_to_le64(iova + j * s->page_size);
|
|
}
|
|
trace_nvme_cmd_map_qiov_iov(s, i, qiov->iov[i].iov_base,
|
|
qiov->iov[i].iov_len / s->page_size);
|
|
}
|
|
|
|
s->dma_map_count += qiov->size;
|
|
|
|
assert(entries <= s->page_size / sizeof(uint64_t));
|
|
switch (entries) {
|
|
case 0:
|
|
abort();
|
|
case 1:
|
|
cmd->prp1 = pagelist[0];
|
|
cmd->prp2 = 0;
|
|
break;
|
|
case 2:
|
|
cmd->prp1 = pagelist[0];
|
|
cmd->prp2 = pagelist[1];
|
|
break;
|
|
default:
|
|
cmd->prp1 = pagelist[0];
|
|
cmd->prp2 = cpu_to_le64(req->prp_list_iova + sizeof(uint64_t));
|
|
break;
|
|
}
|
|
trace_nvme_cmd_map_qiov(s, cmd, req, qiov, entries);
|
|
for (i = 0; i < entries; ++i) {
|
|
trace_nvme_cmd_map_qiov_pages(s, i, pagelist[i]);
|
|
}
|
|
return 0;
|
|
fail:
|
|
/* No need to unmap [0 - i) iovs even if we've failed, since we don't
|
|
* increment s->dma_map_count. This is okay for fixed mapping memory areas
|
|
* because they are already mapped before calling this function; for
|
|
* temporary mappings, a later nvme_cmd_(un)map_qiov will reclaim by
|
|
* calling qemu_vfio_dma_reset_temporary when necessary. */
|
|
return r;
|
|
}
|
|
|
|
typedef struct {
|
|
Coroutine *co;
|
|
int ret;
|
|
AioContext *ctx;
|
|
} NVMeCoData;
|
|
|
|
static void nvme_rw_cb_bh(void *opaque)
|
|
{
|
|
NVMeCoData *data = opaque;
|
|
qemu_coroutine_enter(data->co);
|
|
}
|
|
|
|
static void nvme_rw_cb(void *opaque, int ret)
|
|
{
|
|
NVMeCoData *data = opaque;
|
|
data->ret = ret;
|
|
if (!data->co) {
|
|
/* The rw coroutine hasn't yielded, don't try to enter. */
|
|
return;
|
|
}
|
|
replay_bh_schedule_oneshot_event(data->ctx, nvme_rw_cb_bh, data);
|
|
}
|
|
|
|
static coroutine_fn int nvme_co_prw_aligned(BlockDriverState *bs,
|
|
uint64_t offset, uint64_t bytes,
|
|
QEMUIOVector *qiov,
|
|
bool is_write,
|
|
int flags)
|
|
{
|
|
int r;
|
|
BDRVNVMeState *s = bs->opaque;
|
|
NVMeQueuePair *ioq = s->queues[1];
|
|
NVMeRequest *req;
|
|
|
|
uint32_t cdw12 = (((bytes >> s->blkshift) - 1) & 0xFFFF) |
|
|
(flags & BDRV_REQ_FUA ? 1 << 30 : 0);
|
|
NvmeCmd cmd = {
|
|
.opcode = is_write ? NVME_CMD_WRITE : NVME_CMD_READ,
|
|
.nsid = cpu_to_le32(s->nsid),
|
|
.cdw10 = cpu_to_le32((offset >> s->blkshift) & 0xFFFFFFFF),
|
|
.cdw11 = cpu_to_le32(((offset >> s->blkshift) >> 32) & 0xFFFFFFFF),
|
|
.cdw12 = cpu_to_le32(cdw12),
|
|
};
|
|
NVMeCoData data = {
|
|
.ctx = bdrv_get_aio_context(bs),
|
|
.ret = -EINPROGRESS,
|
|
};
|
|
|
|
trace_nvme_prw_aligned(s, is_write, offset, bytes, flags, qiov->niov);
|
|
assert(s->nr_queues > 1);
|
|
req = nvme_get_free_req(ioq);
|
|
assert(req);
|
|
|
|
qemu_co_mutex_lock(&s->dma_map_lock);
|
|
r = nvme_cmd_map_qiov(bs, &cmd, req, qiov);
|
|
qemu_co_mutex_unlock(&s->dma_map_lock);
|
|
if (r) {
|
|
req->busy = false;
|
|
return r;
|
|
}
|
|
nvme_submit_command(s, ioq, req, &cmd, nvme_rw_cb, &data);
|
|
|
|
data.co = qemu_coroutine_self();
|
|
while (data.ret == -EINPROGRESS) {
|
|
qemu_coroutine_yield();
|
|
}
|
|
|
|
qemu_co_mutex_lock(&s->dma_map_lock);
|
|
r = nvme_cmd_unmap_qiov(bs, qiov);
|
|
qemu_co_mutex_unlock(&s->dma_map_lock);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
|
|
trace_nvme_rw_done(s, is_write, offset, bytes, data.ret);
|
|
return data.ret;
|
|
}
|
|
|
|
static inline bool nvme_qiov_aligned(BlockDriverState *bs,
|
|
const QEMUIOVector *qiov)
|
|
{
|
|
int i;
|
|
BDRVNVMeState *s = bs->opaque;
|
|
|
|
for (i = 0; i < qiov->niov; ++i) {
|
|
if (!QEMU_PTR_IS_ALIGNED(qiov->iov[i].iov_base, s->page_size) ||
|
|
!QEMU_IS_ALIGNED(qiov->iov[i].iov_len, s->page_size)) {
|
|
trace_nvme_qiov_unaligned(qiov, i, qiov->iov[i].iov_base,
|
|
qiov->iov[i].iov_len, s->page_size);
|
|
return false;
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
static int nvme_co_prw(BlockDriverState *bs, uint64_t offset, uint64_t bytes,
|
|
QEMUIOVector *qiov, bool is_write, int flags)
|
|
{
|
|
BDRVNVMeState *s = bs->opaque;
|
|
int r;
|
|
uint8_t *buf = NULL;
|
|
QEMUIOVector local_qiov;
|
|
|
|
assert(QEMU_IS_ALIGNED(offset, s->page_size));
|
|
assert(QEMU_IS_ALIGNED(bytes, s->page_size));
|
|
assert(bytes <= s->max_transfer);
|
|
if (nvme_qiov_aligned(bs, qiov)) {
|
|
return nvme_co_prw_aligned(bs, offset, bytes, qiov, is_write, flags);
|
|
}
|
|
trace_nvme_prw_buffered(s, offset, bytes, qiov->niov, is_write);
|
|
buf = qemu_try_blockalign(bs, bytes);
|
|
|
|
if (!buf) {
|
|
return -ENOMEM;
|
|
}
|
|
qemu_iovec_init(&local_qiov, 1);
|
|
if (is_write) {
|
|
qemu_iovec_to_buf(qiov, 0, buf, bytes);
|
|
}
|
|
qemu_iovec_add(&local_qiov, buf, bytes);
|
|
r = nvme_co_prw_aligned(bs, offset, bytes, &local_qiov, is_write, flags);
|
|
qemu_iovec_destroy(&local_qiov);
|
|
if (!r && !is_write) {
|
|
qemu_iovec_from_buf(qiov, 0, buf, bytes);
|
|
}
|
|
qemu_vfree(buf);
|
|
return r;
|
|
}
|
|
|
|
static coroutine_fn int nvme_co_preadv(BlockDriverState *bs,
|
|
uint64_t offset, uint64_t bytes,
|
|
QEMUIOVector *qiov, int flags)
|
|
{
|
|
return nvme_co_prw(bs, offset, bytes, qiov, false, flags);
|
|
}
|
|
|
|
static coroutine_fn int nvme_co_pwritev(BlockDriverState *bs,
|
|
uint64_t offset, uint64_t bytes,
|
|
QEMUIOVector *qiov, int flags)
|
|
{
|
|
return nvme_co_prw(bs, offset, bytes, qiov, true, flags);
|
|
}
|
|
|
|
static coroutine_fn int nvme_co_flush(BlockDriverState *bs)
|
|
{
|
|
BDRVNVMeState *s = bs->opaque;
|
|
NVMeQueuePair *ioq = s->queues[1];
|
|
NVMeRequest *req;
|
|
NvmeCmd cmd = {
|
|
.opcode = NVME_CMD_FLUSH,
|
|
.nsid = cpu_to_le32(s->nsid),
|
|
};
|
|
NVMeCoData data = {
|
|
.ctx = bdrv_get_aio_context(bs),
|
|
.ret = -EINPROGRESS,
|
|
};
|
|
|
|
assert(s->nr_queues > 1);
|
|
req = nvme_get_free_req(ioq);
|
|
assert(req);
|
|
nvme_submit_command(s, ioq, req, &cmd, nvme_rw_cb, &data);
|
|
|
|
data.co = qemu_coroutine_self();
|
|
if (data.ret == -EINPROGRESS) {
|
|
qemu_coroutine_yield();
|
|
}
|
|
|
|
return data.ret;
|
|
}
|
|
|
|
|
|
static coroutine_fn int nvme_co_pwrite_zeroes(BlockDriverState *bs,
|
|
int64_t offset,
|
|
int bytes,
|
|
BdrvRequestFlags flags)
|
|
{
|
|
BDRVNVMeState *s = bs->opaque;
|
|
NVMeQueuePair *ioq = s->queues[1];
|
|
NVMeRequest *req;
|
|
|
|
uint32_t cdw12 = ((bytes >> s->blkshift) - 1) & 0xFFFF;
|
|
|
|
if (!s->supports_write_zeroes) {
|
|
return -ENOTSUP;
|
|
}
|
|
|
|
NvmeCmd cmd = {
|
|
.opcode = NVME_CMD_WRITE_ZEROS,
|
|
.nsid = cpu_to_le32(s->nsid),
|
|
.cdw10 = cpu_to_le32((offset >> s->blkshift) & 0xFFFFFFFF),
|
|
.cdw11 = cpu_to_le32(((offset >> s->blkshift) >> 32) & 0xFFFFFFFF),
|
|
};
|
|
|
|
NVMeCoData data = {
|
|
.ctx = bdrv_get_aio_context(bs),
|
|
.ret = -EINPROGRESS,
|
|
};
|
|
|
|
if (flags & BDRV_REQ_MAY_UNMAP) {
|
|
cdw12 |= (1 << 25);
|
|
}
|
|
|
|
if (flags & BDRV_REQ_FUA) {
|
|
cdw12 |= (1 << 30);
|
|
}
|
|
|
|
cmd.cdw12 = cpu_to_le32(cdw12);
|
|
|
|
trace_nvme_write_zeroes(s, offset, bytes, flags);
|
|
assert(s->nr_queues > 1);
|
|
req = nvme_get_free_req(ioq);
|
|
assert(req);
|
|
|
|
nvme_submit_command(s, ioq, req, &cmd, nvme_rw_cb, &data);
|
|
|
|
data.co = qemu_coroutine_self();
|
|
while (data.ret == -EINPROGRESS) {
|
|
qemu_coroutine_yield();
|
|
}
|
|
|
|
trace_nvme_rw_done(s, true, offset, bytes, data.ret);
|
|
return data.ret;
|
|
}
|
|
|
|
|
|
static int coroutine_fn nvme_co_pdiscard(BlockDriverState *bs,
|
|
int64_t offset,
|
|
int bytes)
|
|
{
|
|
BDRVNVMeState *s = bs->opaque;
|
|
NVMeQueuePair *ioq = s->queues[1];
|
|
NVMeRequest *req;
|
|
NvmeDsmRange *buf;
|
|
QEMUIOVector local_qiov;
|
|
int ret;
|
|
|
|
NvmeCmd cmd = {
|
|
.opcode = NVME_CMD_DSM,
|
|
.nsid = cpu_to_le32(s->nsid),
|
|
.cdw10 = cpu_to_le32(0), /*number of ranges - 0 based*/
|
|
.cdw11 = cpu_to_le32(1 << 2), /*deallocate bit*/
|
|
};
|
|
|
|
NVMeCoData data = {
|
|
.ctx = bdrv_get_aio_context(bs),
|
|
.ret = -EINPROGRESS,
|
|
};
|
|
|
|
if (!s->supports_discard) {
|
|
return -ENOTSUP;
|
|
}
|
|
|
|
assert(s->nr_queues > 1);
|
|
|
|
buf = qemu_try_blockalign0(bs, s->page_size);
|
|
if (!buf) {
|
|
return -ENOMEM;
|
|
}
|
|
|
|
buf->nlb = cpu_to_le32(bytes >> s->blkshift);
|
|
buf->slba = cpu_to_le64(offset >> s->blkshift);
|
|
buf->cattr = 0;
|
|
|
|
qemu_iovec_init(&local_qiov, 1);
|
|
qemu_iovec_add(&local_qiov, buf, 4096);
|
|
|
|
req = nvme_get_free_req(ioq);
|
|
assert(req);
|
|
|
|
qemu_co_mutex_lock(&s->dma_map_lock);
|
|
ret = nvme_cmd_map_qiov(bs, &cmd, req, &local_qiov);
|
|
qemu_co_mutex_unlock(&s->dma_map_lock);
|
|
|
|
if (ret) {
|
|
req->busy = false;
|
|
goto out;
|
|
}
|
|
|
|
trace_nvme_dsm(s, offset, bytes);
|
|
|
|
nvme_submit_command(s, ioq, req, &cmd, nvme_rw_cb, &data);
|
|
|
|
data.co = qemu_coroutine_self();
|
|
while (data.ret == -EINPROGRESS) {
|
|
qemu_coroutine_yield();
|
|
}
|
|
|
|
qemu_co_mutex_lock(&s->dma_map_lock);
|
|
ret = nvme_cmd_unmap_qiov(bs, &local_qiov);
|
|
qemu_co_mutex_unlock(&s->dma_map_lock);
|
|
|
|
if (ret) {
|
|
goto out;
|
|
}
|
|
|
|
ret = data.ret;
|
|
trace_nvme_dsm_done(s, offset, bytes, ret);
|
|
out:
|
|
qemu_iovec_destroy(&local_qiov);
|
|
qemu_vfree(buf);
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
static int nvme_reopen_prepare(BDRVReopenState *reopen_state,
|
|
BlockReopenQueue *queue, Error **errp)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static void nvme_refresh_filename(BlockDriverState *bs)
|
|
{
|
|
BDRVNVMeState *s = bs->opaque;
|
|
|
|
snprintf(bs->exact_filename, sizeof(bs->exact_filename), "nvme://%s/%i",
|
|
s->device, s->nsid);
|
|
}
|
|
|
|
static void nvme_refresh_limits(BlockDriverState *bs, Error **errp)
|
|
{
|
|
BDRVNVMeState *s = bs->opaque;
|
|
|
|
bs->bl.opt_mem_alignment = s->page_size;
|
|
bs->bl.request_alignment = s->page_size;
|
|
bs->bl.max_transfer = s->max_transfer;
|
|
}
|
|
|
|
static void nvme_detach_aio_context(BlockDriverState *bs)
|
|
{
|
|
BDRVNVMeState *s = bs->opaque;
|
|
|
|
aio_set_event_notifier(bdrv_get_aio_context(bs), &s->irq_notifier,
|
|
false, NULL, NULL);
|
|
}
|
|
|
|
static void nvme_attach_aio_context(BlockDriverState *bs,
|
|
AioContext *new_context)
|
|
{
|
|
BDRVNVMeState *s = bs->opaque;
|
|
|
|
s->aio_context = new_context;
|
|
aio_set_event_notifier(new_context, &s->irq_notifier,
|
|
false, nvme_handle_event, nvme_poll_cb);
|
|
}
|
|
|
|
static void nvme_aio_plug(BlockDriverState *bs)
|
|
{
|
|
BDRVNVMeState *s = bs->opaque;
|
|
assert(!s->plugged);
|
|
s->plugged = true;
|
|
}
|
|
|
|
static void nvme_aio_unplug(BlockDriverState *bs)
|
|
{
|
|
int i;
|
|
BDRVNVMeState *s = bs->opaque;
|
|
assert(s->plugged);
|
|
s->plugged = false;
|
|
for (i = 1; i < s->nr_queues; i++) {
|
|
NVMeQueuePair *q = s->queues[i];
|
|
qemu_mutex_lock(&q->lock);
|
|
nvme_kick(s, q);
|
|
nvme_process_completion(s, q);
|
|
qemu_mutex_unlock(&q->lock);
|
|
}
|
|
}
|
|
|
|
static void nvme_register_buf(BlockDriverState *bs, void *host, size_t size)
|
|
{
|
|
int ret;
|
|
BDRVNVMeState *s = bs->opaque;
|
|
|
|
ret = qemu_vfio_dma_map(s->vfio, host, size, false, NULL);
|
|
if (ret) {
|
|
/* FIXME: we may run out of IOVA addresses after repeated
|
|
* bdrv_register_buf/bdrv_unregister_buf, because nvme_vfio_dma_unmap
|
|
* doesn't reclaim addresses for fixed mappings. */
|
|
error_report("nvme_register_buf failed: %s", strerror(-ret));
|
|
}
|
|
}
|
|
|
|
static void nvme_unregister_buf(BlockDriverState *bs, void *host)
|
|
{
|
|
BDRVNVMeState *s = bs->opaque;
|
|
|
|
qemu_vfio_dma_unmap(s->vfio, host);
|
|
}
|
|
|
|
static const char *const nvme_strong_runtime_opts[] = {
|
|
NVME_BLOCK_OPT_DEVICE,
|
|
NVME_BLOCK_OPT_NAMESPACE,
|
|
|
|
NULL
|
|
};
|
|
|
|
static BlockDriver bdrv_nvme = {
|
|
.format_name = "nvme",
|
|
.protocol_name = "nvme",
|
|
.instance_size = sizeof(BDRVNVMeState),
|
|
|
|
.bdrv_co_create_opts = bdrv_co_create_opts_simple,
|
|
.create_opts = &bdrv_create_opts_simple,
|
|
|
|
.bdrv_parse_filename = nvme_parse_filename,
|
|
.bdrv_file_open = nvme_file_open,
|
|
.bdrv_close = nvme_close,
|
|
.bdrv_getlength = nvme_getlength,
|
|
.bdrv_probe_blocksizes = nvme_probe_blocksizes,
|
|
|
|
.bdrv_co_preadv = nvme_co_preadv,
|
|
.bdrv_co_pwritev = nvme_co_pwritev,
|
|
|
|
.bdrv_co_pwrite_zeroes = nvme_co_pwrite_zeroes,
|
|
.bdrv_co_pdiscard = nvme_co_pdiscard,
|
|
|
|
.bdrv_co_flush_to_disk = nvme_co_flush,
|
|
.bdrv_reopen_prepare = nvme_reopen_prepare,
|
|
|
|
.bdrv_refresh_filename = nvme_refresh_filename,
|
|
.bdrv_refresh_limits = nvme_refresh_limits,
|
|
.strong_runtime_opts = nvme_strong_runtime_opts,
|
|
|
|
.bdrv_detach_aio_context = nvme_detach_aio_context,
|
|
.bdrv_attach_aio_context = nvme_attach_aio_context,
|
|
|
|
.bdrv_io_plug = nvme_aio_plug,
|
|
.bdrv_io_unplug = nvme_aio_unplug,
|
|
|
|
.bdrv_register_buf = nvme_register_buf,
|
|
.bdrv_unregister_buf = nvme_unregister_buf,
|
|
};
|
|
|
|
static void bdrv_nvme_init(void)
|
|
{
|
|
bdrv_register(&bdrv_nvme);
|
|
}
|
|
|
|
block_init(bdrv_nvme_init);
|