git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2158 c046a42c-6fe2-441c-8c8c-71466251a162
559 lines
14 KiB
C
559 lines
14 KiB
C
/*
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* QEMU ESP/NCR53C9x emulation
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*
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* Copyright (c) 2005-2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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/* debug ESP card */
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//#define DEBUG_ESP
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/*
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* On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), also
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* produced as NCR89C100. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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* and
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
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*/
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#ifdef DEBUG_ESP
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#define DPRINTF(fmt, args...) \
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do { printf("ESP: " fmt , ##args); } while (0)
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#else
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#define DPRINTF(fmt, args...)
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#endif
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#define ESP_MAXREG 0x3f
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#define TI_BUFSZ 32
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typedef struct ESPState ESPState;
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struct ESPState {
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BlockDriverState **bd;
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uint8_t rregs[ESP_MAXREG];
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uint8_t wregs[ESP_MAXREG];
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int32_t ti_size;
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uint32_t ti_rptr, ti_wptr;
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uint8_t ti_buf[TI_BUFSZ];
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int sense;
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int dma;
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SCSIDevice *scsi_dev[MAX_DISKS];
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SCSIDevice *current_dev;
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uint8_t cmdbuf[TI_BUFSZ];
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int cmdlen;
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int do_cmd;
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/* The amount of data left in the current DMA transfer. */
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uint32_t dma_left;
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/* The size of the current DMA transfer. Zero if no transfer is in
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progress. */
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uint32_t dma_counter;
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uint8_t *async_buf;
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uint32_t async_len;
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void *dma_opaque;
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};
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#define STAT_DO 0x00
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#define STAT_DI 0x01
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#define STAT_CD 0x02
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#define STAT_ST 0x03
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#define STAT_MI 0x06
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#define STAT_MO 0x07
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#define STAT_TC 0x10
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#define STAT_PE 0x20
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#define STAT_GE 0x40
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#define STAT_IN 0x80
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#define INTR_FC 0x08
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#define INTR_BS 0x10
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#define INTR_DC 0x20
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#define INTR_RST 0x80
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#define SEQ_0 0x0
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#define SEQ_CD 0x4
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static int get_cmd(ESPState *s, uint8_t *buf)
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{
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uint32_t dmalen;
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int target;
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dmalen = s->rregs[0] | (s->rregs[1] << 8);
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target = s->wregs[4] & 7;
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DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
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if (s->dma) {
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espdma_memory_read(s->dma_opaque, buf, dmalen);
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} else {
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buf[0] = 0;
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memcpy(&buf[1], s->ti_buf, dmalen);
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dmalen++;
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}
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s->ti_size = 0;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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if (s->current_dev) {
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/* Started a new command before the old one finished. Cancel it. */
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scsi_cancel_io(s->current_dev, 0);
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s->async_len = 0;
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}
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if (target >= MAX_DISKS || !s->scsi_dev[target]) {
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// No such drive
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s->rregs[4] = STAT_IN;
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s->rregs[5] = INTR_DC;
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s->rregs[6] = SEQ_0;
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espdma_raise_irq(s->dma_opaque);
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return 0;
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}
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s->current_dev = s->scsi_dev[target];
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return dmalen;
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}
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static void do_cmd(ESPState *s, uint8_t *buf)
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{
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int32_t datalen;
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int lun;
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DPRINTF("do_cmd: busid 0x%x\n", buf[0]);
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lun = buf[0] & 7;
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datalen = scsi_send_command(s->current_dev, 0, &buf[1], lun);
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s->ti_size = datalen;
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if (datalen != 0) {
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s->rregs[4] = STAT_IN | STAT_TC;
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s->dma_left = 0;
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s->dma_counter = 0;
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if (datalen > 0) {
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s->rregs[4] |= STAT_DI;
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scsi_read_data(s->current_dev, 0);
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} else {
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s->rregs[4] |= STAT_DO;
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scsi_write_data(s->current_dev, 0);
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}
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}
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s->rregs[5] = INTR_BS | INTR_FC;
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s->rregs[6] = SEQ_CD;
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espdma_raise_irq(s->dma_opaque);
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}
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static void handle_satn(ESPState *s)
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{
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uint8_t buf[32];
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int len;
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len = get_cmd(s, buf);
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if (len)
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do_cmd(s, buf);
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}
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static void handle_satn_stop(ESPState *s)
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{
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s->cmdlen = get_cmd(s, s->cmdbuf);
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if (s->cmdlen) {
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DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
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s->do_cmd = 1;
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s->rregs[4] = STAT_IN | STAT_TC | STAT_CD;
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s->rregs[5] = INTR_BS | INTR_FC;
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s->rregs[6] = SEQ_CD;
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espdma_raise_irq(s->dma_opaque);
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}
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}
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static void write_response(ESPState *s)
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{
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DPRINTF("Transfer status (sense=%d)\n", s->sense);
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s->ti_buf[0] = s->sense;
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s->ti_buf[1] = 0;
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if (s->dma) {
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espdma_memory_write(s->dma_opaque, s->ti_buf, 2);
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s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
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s->rregs[5] = INTR_BS | INTR_FC;
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s->rregs[6] = SEQ_CD;
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} else {
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s->ti_size = 2;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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s->rregs[7] = 2;
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}
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espdma_raise_irq(s->dma_opaque);
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}
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static void esp_dma_done(ESPState *s)
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{
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s->rregs[4] |= STAT_IN | STAT_TC;
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s->rregs[5] = INTR_BS;
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s->rregs[6] = 0;
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s->rregs[7] = 0;
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s->rregs[0] = 0;
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s->rregs[1] = 0;
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espdma_raise_irq(s->dma_opaque);
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}
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static void esp_do_dma(ESPState *s)
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{
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uint32_t len;
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int to_device;
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to_device = (s->ti_size < 0);
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len = s->dma_left;
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if (s->do_cmd) {
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DPRINTF("command len %d + %d\n", s->cmdlen, len);
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espdma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
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s->ti_size = 0;
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s->cmdlen = 0;
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s->do_cmd = 0;
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do_cmd(s, s->cmdbuf);
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return;
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}
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if (s->async_len == 0) {
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/* Defer until data is available. */
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return;
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}
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if (len > s->async_len) {
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len = s->async_len;
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}
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if (to_device) {
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espdma_memory_read(s->dma_opaque, s->async_buf, len);
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} else {
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espdma_memory_write(s->dma_opaque, s->async_buf, len);
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}
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s->dma_left -= len;
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s->async_buf += len;
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s->async_len -= len;
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if (to_device)
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s->ti_size += len;
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else
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s->ti_size -= len;
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if (s->async_len == 0) {
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if (to_device) {
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// ti_size is negative
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scsi_write_data(s->current_dev, 0);
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} else {
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scsi_read_data(s->current_dev, 0);
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/* If there is still data to be read from the device then
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complete the DMA operation immeriately. Otherwise defer
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until the scsi layer has completed. */
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if (s->dma_left == 0 && s->ti_size > 0) {
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esp_dma_done(s);
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}
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}
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} else {
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/* Partially filled a scsi buffer. Complete immediately. */
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esp_dma_done(s);
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}
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}
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static void esp_command_complete(void *opaque, int reason, uint32_t tag,
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uint32_t arg)
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{
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ESPState *s = (ESPState *)opaque;
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if (reason == SCSI_REASON_DONE) {
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DPRINTF("SCSI Command complete\n");
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if (s->ti_size != 0)
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DPRINTF("SCSI command completed unexpectedly\n");
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s->ti_size = 0;
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s->dma_left = 0;
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s->async_len = 0;
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if (arg)
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DPRINTF("Command failed\n");
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s->sense = arg;
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s->rregs[4] = STAT_ST;
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esp_dma_done(s);
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s->current_dev = NULL;
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} else {
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DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size);
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s->async_len = arg;
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s->async_buf = scsi_get_buf(s->current_dev, 0);
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if (s->dma_left) {
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esp_do_dma(s);
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} else if (s->dma_counter != 0 && s->ti_size <= 0) {
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/* If this was the last part of a DMA transfer then the
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completion interrupt is deferred to here. */
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esp_dma_done(s);
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}
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}
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}
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static void handle_ti(ESPState *s)
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{
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uint32_t dmalen, minlen;
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dmalen = s->rregs[0] | (s->rregs[1] << 8);
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if (dmalen==0) {
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dmalen=0x10000;
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}
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s->dma_counter = dmalen;
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if (s->do_cmd)
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minlen = (dmalen < 32) ? dmalen : 32;
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else if (s->ti_size < 0)
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minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
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else
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minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
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DPRINTF("Transfer Information len %d\n", minlen);
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if (s->dma) {
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s->dma_left = minlen;
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s->rregs[4] &= ~STAT_TC;
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esp_do_dma(s);
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} else if (s->do_cmd) {
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DPRINTF("command len %d\n", s->cmdlen);
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s->ti_size = 0;
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s->cmdlen = 0;
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s->do_cmd = 0;
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do_cmd(s, s->cmdbuf);
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return;
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}
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}
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void esp_reset(void *opaque)
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{
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ESPState *s = opaque;
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memset(s->rregs, 0, ESP_MAXREG);
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memset(s->wregs, 0, ESP_MAXREG);
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s->rregs[0x0e] = 0x4; // Indicate fas100a
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s->ti_size = 0;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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s->dma = 0;
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s->do_cmd = 0;
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}
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static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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ESPState *s = opaque;
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uint32_t saddr;
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saddr = (addr & ESP_MAXREG) >> 2;
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DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
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switch (saddr) {
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case 2:
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// FIFO
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if (s->ti_size > 0) {
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s->ti_size--;
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if ((s->rregs[4] & 6) == 0) {
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/* Data in/out. */
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fprintf(stderr, "esp: PIO data read not implemented\n");
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s->rregs[2] = 0;
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} else {
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s->rregs[2] = s->ti_buf[s->ti_rptr++];
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}
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espdma_raise_irq(s->dma_opaque);
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}
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if (s->ti_size == 0) {
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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}
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break;
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case 5:
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// interrupt
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// Clear interrupt/error status bits
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s->rregs[4] &= ~(STAT_IN | STAT_GE | STAT_PE);
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espdma_clear_irq(s->dma_opaque);
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break;
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default:
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break;
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}
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return s->rregs[saddr];
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}
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static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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ESPState *s = opaque;
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uint32_t saddr;
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saddr = (addr & ESP_MAXREG) >> 2;
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DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr], val);
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switch (saddr) {
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case 0:
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case 1:
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s->rregs[4] &= ~STAT_TC;
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break;
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case 2:
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// FIFO
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if (s->do_cmd) {
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s->cmdbuf[s->cmdlen++] = val & 0xff;
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} else if ((s->rregs[4] & 6) == 0) {
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uint8_t buf;
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buf = val & 0xff;
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s->ti_size--;
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fprintf(stderr, "esp: PIO data write not implemented\n");
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} else {
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s->ti_size++;
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s->ti_buf[s->ti_wptr++] = val & 0xff;
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}
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break;
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case 3:
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s->rregs[saddr] = val;
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// Command
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if (val & 0x80) {
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s->dma = 1;
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/* Reload DMA counter. */
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s->rregs[0] = s->wregs[0];
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s->rregs[1] = s->wregs[1];
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} else {
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s->dma = 0;
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}
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switch(val & 0x7f) {
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case 0:
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DPRINTF("NOP (%2.2x)\n", val);
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break;
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case 1:
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DPRINTF("Flush FIFO (%2.2x)\n", val);
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//s->ti_size = 0;
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s->rregs[5] = INTR_FC;
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s->rregs[6] = 0;
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break;
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case 2:
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DPRINTF("Chip reset (%2.2x)\n", val);
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esp_reset(s);
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break;
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case 3:
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DPRINTF("Bus reset (%2.2x)\n", val);
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s->rregs[5] = INTR_RST;
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if (!(s->wregs[8] & 0x40)) {
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espdma_raise_irq(s->dma_opaque);
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}
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break;
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case 0x10:
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handle_ti(s);
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break;
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case 0x11:
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DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
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write_response(s);
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break;
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case 0x12:
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DPRINTF("Message Accepted (%2.2x)\n", val);
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write_response(s);
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s->rregs[5] = INTR_DC;
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s->rregs[6] = 0;
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break;
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case 0x1a:
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DPRINTF("Set ATN (%2.2x)\n", val);
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break;
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case 0x42:
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DPRINTF("Set ATN (%2.2x)\n", val);
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handle_satn(s);
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break;
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case 0x43:
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DPRINTF("Set ATN & stop (%2.2x)\n", val);
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handle_satn_stop(s);
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break;
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default:
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DPRINTF("Unhandled ESP command (%2.2x)\n", val);
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break;
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}
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break;
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case 4 ... 7:
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break;
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case 8:
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s->rregs[saddr] = val;
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break;
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case 9 ... 10:
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break;
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case 11:
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s->rregs[saddr] = val & 0x15;
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break;
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case 12 ... 15:
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s->rregs[saddr] = val;
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break;
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default:
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break;
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}
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s->wregs[saddr] = val;
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}
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static CPUReadMemoryFunc *esp_mem_read[3] = {
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esp_mem_readb,
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esp_mem_readb,
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esp_mem_readb,
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};
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static CPUWriteMemoryFunc *esp_mem_write[3] = {
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esp_mem_writeb,
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esp_mem_writeb,
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esp_mem_writeb,
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};
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static void esp_save(QEMUFile *f, void *opaque)
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{
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ESPState *s = opaque;
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qemu_put_buffer(f, s->rregs, ESP_MAXREG);
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qemu_put_buffer(f, s->wregs, ESP_MAXREG);
|
|
qemu_put_be32s(f, &s->ti_size);
|
|
qemu_put_be32s(f, &s->ti_rptr);
|
|
qemu_put_be32s(f, &s->ti_wptr);
|
|
qemu_put_buffer(f, s->ti_buf, TI_BUFSZ);
|
|
qemu_put_be32s(f, &s->dma);
|
|
}
|
|
|
|
static int esp_load(QEMUFile *f, void *opaque, int version_id)
|
|
{
|
|
ESPState *s = opaque;
|
|
|
|
if (version_id != 2)
|
|
return -EINVAL; // Cannot emulate 1
|
|
|
|
qemu_get_buffer(f, s->rregs, ESP_MAXREG);
|
|
qemu_get_buffer(f, s->wregs, ESP_MAXREG);
|
|
qemu_get_be32s(f, &s->ti_size);
|
|
qemu_get_be32s(f, &s->ti_rptr);
|
|
qemu_get_be32s(f, &s->ti_wptr);
|
|
qemu_get_buffer(f, s->ti_buf, TI_BUFSZ);
|
|
qemu_get_be32s(f, &s->dma);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void *esp_init(BlockDriverState **bd, uint32_t espaddr, void *dma_opaque)
|
|
{
|
|
ESPState *s;
|
|
int esp_io_memory;
|
|
int i;
|
|
|
|
s = qemu_mallocz(sizeof(ESPState));
|
|
if (!s)
|
|
return NULL;
|
|
|
|
s->bd = bd;
|
|
s->dma_opaque = dma_opaque;
|
|
|
|
esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);
|
|
cpu_register_physical_memory(espaddr, ESP_MAXREG*4, esp_io_memory);
|
|
|
|
esp_reset(s);
|
|
|
|
register_savevm("esp", espaddr, 2, esp_save, esp_load, s);
|
|
qemu_register_reset(esp_reset, s);
|
|
for (i = 0; i < MAX_DISKS; i++) {
|
|
if (bs_table[i]) {
|
|
/* Command queueing is not implemented. */
|
|
s->scsi_dev[i] =
|
|
scsi_disk_init(bs_table[i], 0, esp_command_complete, s);
|
|
}
|
|
}
|
|
|
|
return s;
|
|
}
|