Stafford Horne 9f6e8afad7 target/openrisc: Fix delay slot exception flag to match spec ... The delay slot exception flag is only set on the SR register during exception. Previously it was being set on both the ESR and SR this caused QEMU to differ from the spec. The was apparent as the linux kernel had a bug where it could boot on QEMU but not on real hardware. The fixed logic now matches hardware. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>		2018-07-03 22:40:33 +09:00
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cpu.c	linux-user: Implement signals for openrisc	2018-07-03 22:40:33 +09:00
cpu.h	target/openrisc: Reorg tlb lookup	2018-07-03 22:40:33 +09:00
disas.c	target/openrisc: Add print_insn_or1k	2018-07-03 00:05:28 +09:00
exception.c	Move target-* CPU file into a target/ folder	2016-12-20 21:52:12 +01:00
exception.h	Move target-* CPU file into a target/ folder	2016-12-20 21:52:12 +01:00
exception_helper.c	misc: remove duplicated includes	2017-12-18 17:07:02 +03:00
fpu_helper.c	target-openrisc: Write back result before FPE exception	2018-05-14 14:35:02 -07:00
gdbstub.c	target/openrisc: implement shadow registers	2017-05-04 09:39:01 +09:00
helper.h	target/openrisc: Form the spr index from tcg	2018-07-03 00:05:28 +09:00
insns.decode	target/openrisc: Convert dec_float	2018-05-14 14:55:29 -07:00
interrupt.c	target/openrisc: Fix delay slot exception flag to match spec	2018-07-03 22:40:33 +09:00
interrupt_helper.c	target/openrisc: Fix cpu_mmu_index	2018-07-03 00:05:28 +09:00
machine.c	target/openrisc: Increase the TLB size	2018-07-03 00:05:28 +09:00
Makefile.objs	target/openrisc: Merge mmu_helper.c into mmu.c	2018-07-03 00:05:28 +09:00
mmu.c	target/openrisc: Reorg tlb lookup	2018-07-03 22:40:33 +09:00
sys_helper.c	target/openrisc: Use identical sizes for ITLB and DTLB	2018-07-03 00:05:28 +09:00
translate.c	target/openrisc: Fix cpu_mmu_index	2018-07-03 00:05:28 +09:00