The IGD quirk code defines a separate device, the so-called "vfio-pci-igd-lpc-bridge" which shows up as a user-creatable device in all QEMU binaries that include the vfio code. This is a little bit unfortunate for two reasons: First, this device is completely useless in binaries like qemu-system-s390x. Second we also would like to disable it in downstream RHEL which currently requires some extra patches there since the device does not have a proper Kconfig-style switch yet. So it would be good if the device could be disabled more easily, thus let's move the code to a separate file instead and introduce a proper Kconfig switch for it which gets only enabled by default if we also have CONFIG_PC_PCI enabled. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
617 lines
21 KiB
C
617 lines
21 KiB
C
/*
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* IGD device quirks
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*
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* Copyright Red Hat, Inc. 2016
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*
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* Authors:
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* Alex Williamson <alex.williamson@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "hw/hw.h"
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#include "hw/nvram/fw_cfg.h"
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#include "pci.h"
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#include "trace.h"
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/*
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* Intel IGD support
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*
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* Obviously IGD is not a discrete device, this is evidenced not only by it
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* being integrated into the CPU, but by the various chipset and BIOS
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* dependencies that it brings along with it. Intel is trying to move away
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* from this and Broadwell and newer devices can run in what Intel calls
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* "Universal Pass-Through" mode, or UPT. Theoretically in UPT mode, nothing
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* more is required beyond assigning the IGD device to a VM. There are
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* however support limitations to this mode. It only supports IGD as a
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* secondary graphics device in the VM and it doesn't officially support any
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* physical outputs.
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*
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* The code here attempts to enable what we'll call legacy mode assignment,
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* IGD retains most of the capabilities we expect for it to have on bare
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* metal. To enable this mode, the IGD device must be assigned to the VM
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* at PCI address 00:02.0, it must have a ROM, it very likely needs VGA
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* support, we must have VM BIOS support for reserving and populating some
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* of the required tables, and we need to tweak the chipset with revisions
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* and IDs and an LPC/ISA bridge device. The intention is to make all of
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* this happen automatically by installing the device at the correct VM PCI
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* bus address. If any of the conditions are not met, we cross our fingers
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* and hope the user knows better.
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*
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* NB - It is possible to enable physical outputs in UPT mode by supplying
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* an OpRegion table. We don't do this by default because the guest driver
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* behaves differently if an OpRegion is provided and no monitor is attached
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* vs no OpRegion and a monitor being attached or not. Effectively, if a
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* headless setup is desired, the OpRegion gets in the way of that.
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*/
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/*
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* This presumes the device is already known to be an Intel VGA device, so we
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* take liberties in which device ID bits match which generation. This should
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* not be taken as an indication that all the devices are supported, or even
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* supportable, some of them don't even support VT-d.
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* See linux:include/drm/i915_pciids.h for IDs.
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*/
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static int igd_gen(VFIOPCIDevice *vdev)
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{
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if ((vdev->device_id & 0xfff) == 0xa84) {
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return 8; /* Broxton */
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}
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switch (vdev->device_id & 0xff00) {
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/* Old, untested, unavailable, unknown */
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case 0x0000:
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case 0x2500:
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case 0x2700:
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case 0x2900:
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case 0x2a00:
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case 0x2e00:
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case 0x3500:
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case 0xa000:
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return -1;
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/* SandyBridge, IvyBridge, ValleyView, Haswell */
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case 0x0100:
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case 0x0400:
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case 0x0a00:
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case 0x0c00:
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case 0x0d00:
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case 0x0f00:
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return 6;
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/* BroadWell, CherryView, SkyLake, KabyLake */
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case 0x1600:
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case 0x1900:
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case 0x2200:
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case 0x5900:
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return 8;
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}
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return 8; /* Assume newer is compatible */
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}
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typedef struct VFIOIGDQuirk {
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struct VFIOPCIDevice *vdev;
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uint32_t index;
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uint32_t bdsm;
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} VFIOIGDQuirk;
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#define IGD_GMCH 0x50 /* Graphics Control Register */
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#define IGD_BDSM 0x5c /* Base Data of Stolen Memory */
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/*
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* The rather short list of registers that we copy from the host devices.
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* The LPC/ISA bridge values are definitely needed to support the vBIOS, the
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* host bridge values may or may not be needed depending on the guest OS.
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* Since we're only munging revision and subsystem values on the host bridge,
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* we don't require our own device. The LPC/ISA bridge needs to be our very
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* own though.
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*/
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typedef struct {
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uint8_t offset;
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uint8_t len;
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} IGDHostInfo;
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static const IGDHostInfo igd_host_bridge_infos[] = {
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{PCI_REVISION_ID, 2},
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{PCI_SUBSYSTEM_VENDOR_ID, 2},
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{PCI_SUBSYSTEM_ID, 2},
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};
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static const IGDHostInfo igd_lpc_bridge_infos[] = {
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{PCI_VENDOR_ID, 2},
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{PCI_DEVICE_ID, 2},
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{PCI_REVISION_ID, 2},
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{PCI_SUBSYSTEM_VENDOR_ID, 2},
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{PCI_SUBSYSTEM_ID, 2},
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};
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static int vfio_pci_igd_copy(VFIOPCIDevice *vdev, PCIDevice *pdev,
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struct vfio_region_info *info,
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const IGDHostInfo *list, int len)
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{
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int i, ret;
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for (i = 0; i < len; i++) {
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ret = pread(vdev->vbasedev.fd, pdev->config + list[i].offset,
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list[i].len, info->offset + list[i].offset);
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if (ret != list[i].len) {
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error_report("IGD copy failed: %m");
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return -errno;
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}
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}
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return 0;
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}
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/*
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* Stuff a few values into the host bridge.
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*/
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static int vfio_pci_igd_host_init(VFIOPCIDevice *vdev,
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struct vfio_region_info *info)
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{
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PCIBus *bus;
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PCIDevice *host_bridge;
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int ret;
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bus = pci_device_root_bus(&vdev->pdev);
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host_bridge = pci_find_device(bus, 0, PCI_DEVFN(0, 0));
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if (!host_bridge) {
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error_report("Can't find host bridge");
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return -ENODEV;
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}
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ret = vfio_pci_igd_copy(vdev, host_bridge, info, igd_host_bridge_infos,
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ARRAY_SIZE(igd_host_bridge_infos));
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if (!ret) {
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trace_vfio_pci_igd_host_bridge_enabled(vdev->vbasedev.name);
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}
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return ret;
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}
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/*
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* IGD LPC/ISA bridge support code. The vBIOS needs this, but we can't write
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* arbitrary values into just any bridge, so we must create our own. We try
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* to handle if the user has created it for us, which they might want to do
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* to enable multifunction so we don't occupy the whole PCI slot.
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*/
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static void vfio_pci_igd_lpc_bridge_realize(PCIDevice *pdev, Error **errp)
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{
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if (pdev->devfn != PCI_DEVFN(0x1f, 0)) {
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error_setg(errp, "VFIO dummy ISA/LPC bridge must have address 1f.0");
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}
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}
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static void vfio_pci_igd_lpc_bridge_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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dc->desc = "VFIO dummy ISA/LPC bridge for IGD assignment";
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dc->hotpluggable = false;
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k->realize = vfio_pci_igd_lpc_bridge_realize;
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k->class_id = PCI_CLASS_BRIDGE_ISA;
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}
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static TypeInfo vfio_pci_igd_lpc_bridge_info = {
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.name = "vfio-pci-igd-lpc-bridge",
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.parent = TYPE_PCI_DEVICE,
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.class_init = vfio_pci_igd_lpc_bridge_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void vfio_pci_igd_register_types(void)
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{
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type_register_static(&vfio_pci_igd_lpc_bridge_info);
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}
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type_init(vfio_pci_igd_register_types)
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static int vfio_pci_igd_lpc_init(VFIOPCIDevice *vdev,
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struct vfio_region_info *info)
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{
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PCIDevice *lpc_bridge;
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int ret;
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lpc_bridge = pci_find_device(pci_device_root_bus(&vdev->pdev),
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0, PCI_DEVFN(0x1f, 0));
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if (!lpc_bridge) {
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lpc_bridge = pci_create_simple(pci_device_root_bus(&vdev->pdev),
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PCI_DEVFN(0x1f, 0), "vfio-pci-igd-lpc-bridge");
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}
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ret = vfio_pci_igd_copy(vdev, lpc_bridge, info, igd_lpc_bridge_infos,
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ARRAY_SIZE(igd_lpc_bridge_infos));
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if (!ret) {
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trace_vfio_pci_igd_lpc_bridge_enabled(vdev->vbasedev.name);
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}
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return ret;
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}
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/*
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* IGD Gen8 and newer support up to 8MB for the GTT and use a 64bit PTE
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* entry, older IGDs use 2MB and 32bit. Each PTE maps a 4k page. Therefore
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* we either have 2M/4k * 4 = 2k or 8M/4k * 8 = 16k as the maximum iobar index
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* for programming the GTT.
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*
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* See linux:include/drm/i915_drm.h for shift and mask values.
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*/
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static int vfio_igd_gtt_max(VFIOPCIDevice *vdev)
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{
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uint32_t gmch = vfio_pci_read_config(&vdev->pdev, IGD_GMCH, sizeof(gmch));
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int ggms, gen = igd_gen(vdev);
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gmch = vfio_pci_read_config(&vdev->pdev, IGD_GMCH, sizeof(gmch));
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ggms = (gmch >> (gen < 8 ? 8 : 6)) & 0x3;
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if (gen > 6) {
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ggms = 1 << ggms;
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}
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ggms *= MiB;
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return (ggms / (4 * KiB)) * (gen < 8 ? 4 : 8);
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}
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/*
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* The IGD ROM will make use of stolen memory (GGMS) for support of VESA modes.
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* Somehow the host stolen memory range is used for this, but how the ROM gets
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* it is a mystery, perhaps it's hardcoded into the ROM. Thankfully though, it
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* reprograms the GTT through the IOBAR where we can trap it and transpose the
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* programming to the VM allocated buffer. That buffer gets reserved by the VM
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* firmware via the fw_cfg entry added below. Here we're just monitoring the
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* IOBAR address and data registers to detect a write sequence targeting the
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* GTTADR. This code is developed by observed behavior and doesn't have a
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* direct spec reference, unfortunately.
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*/
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static uint64_t vfio_igd_quirk_data_read(void *opaque,
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hwaddr addr, unsigned size)
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{
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VFIOIGDQuirk *igd = opaque;
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VFIOPCIDevice *vdev = igd->vdev;
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igd->index = ~0;
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return vfio_region_read(&vdev->bars[4].region, addr + 4, size);
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}
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static void vfio_igd_quirk_data_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned size)
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{
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VFIOIGDQuirk *igd = opaque;
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VFIOPCIDevice *vdev = igd->vdev;
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uint64_t val = data;
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int gen = igd_gen(vdev);
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/*
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* Programming the GGMS starts at index 0x1 and uses every 4th index (ie.
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* 0x1, 0x5, 0x9, 0xd,...). For pre-Gen8 each 4-byte write is a whole PTE
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* entry, with 0th bit enable set. For Gen8 and up, PTEs are 64bit, so
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* entries 0x5 & 0xd are the high dword, in our case zero. Each PTE points
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* to a 4k page, which we translate to a page from the VM allocated region,
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* pointed to by the BDSM register. If this is not set, we fail.
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*
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* We trap writes to the full configured GTT size, but we typically only
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* see the vBIOS writing up to (nearly) the 1MB barrier. In fact it often
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* seems to miss the last entry for an even 1MB GTT. Doing a gratuitous
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* write of that last entry does work, but is hopefully unnecessary since
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* we clear the previous GTT on initialization.
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*/
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if ((igd->index % 4 == 1) && igd->index < vfio_igd_gtt_max(vdev)) {
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if (gen < 8 || (igd->index % 8 == 1)) {
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uint32_t base;
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base = pci_get_long(vdev->pdev.config + IGD_BDSM);
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if (!base) {
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hw_error("vfio-igd: Guest attempted to program IGD GTT before "
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"BIOS reserved stolen memory. Unsupported BIOS?");
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}
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val = data - igd->bdsm + base;
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} else {
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val = 0; /* upper 32bits of pte, we only enable below 4G PTEs */
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}
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trace_vfio_pci_igd_bar4_write(vdev->vbasedev.name,
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igd->index, data, val);
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}
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vfio_region_write(&vdev->bars[4].region, addr + 4, val, size);
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igd->index = ~0;
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}
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static const MemoryRegionOps vfio_igd_data_quirk = {
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.read = vfio_igd_quirk_data_read,
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.write = vfio_igd_quirk_data_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static uint64_t vfio_igd_quirk_index_read(void *opaque,
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hwaddr addr, unsigned size)
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{
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VFIOIGDQuirk *igd = opaque;
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VFIOPCIDevice *vdev = igd->vdev;
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igd->index = ~0;
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return vfio_region_read(&vdev->bars[4].region, addr, size);
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}
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static void vfio_igd_quirk_index_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned size)
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{
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VFIOIGDQuirk *igd = opaque;
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VFIOPCIDevice *vdev = igd->vdev;
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igd->index = data;
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vfio_region_write(&vdev->bars[4].region, addr, data, size);
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}
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static const MemoryRegionOps vfio_igd_index_quirk = {
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.read = vfio_igd_quirk_index_read,
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.write = vfio_igd_quirk_index_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int nr)
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{
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struct vfio_region_info *rom = NULL, *opregion = NULL,
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*host = NULL, *lpc = NULL;
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VFIOQuirk *quirk;
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VFIOIGDQuirk *igd;
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PCIDevice *lpc_bridge;
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int i, ret, ggms_mb, gms_mb = 0, gen;
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uint64_t *bdsm_size;
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uint32_t gmch;
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uint16_t cmd_orig, cmd;
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Error *err = NULL;
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/*
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* This must be an Intel VGA device at address 00:02.0 for us to even
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* consider enabling legacy mode. The vBIOS has dependencies on the
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* PCI bus address.
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*/
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if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) ||
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!vfio_is_vga(vdev) || nr != 4 ||
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&vdev->pdev != pci_find_device(pci_device_root_bus(&vdev->pdev),
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0, PCI_DEVFN(0x2, 0))) {
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return;
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}
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/*
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* We need to create an LPC/ISA bridge at PCI bus address 00:1f.0 that we
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* can stuff host values into, so if there's already one there and it's not
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* one we can hack on, legacy mode is no-go. Sorry Q35.
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*/
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lpc_bridge = pci_find_device(pci_device_root_bus(&vdev->pdev),
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0, PCI_DEVFN(0x1f, 0));
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if (lpc_bridge && !object_dynamic_cast(OBJECT(lpc_bridge),
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"vfio-pci-igd-lpc-bridge")) {
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error_report("IGD device %s cannot support legacy mode due to existing "
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"devices at address 1f.0", vdev->vbasedev.name);
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return;
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}
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/*
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* IGD is not a standard, they like to change their specs often. We
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* only attempt to support back to SandBridge and we hope that newer
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* devices maintain compatibility with generation 8.
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*/
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gen = igd_gen(vdev);
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if (gen != 6 && gen != 8) {
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error_report("IGD device %s is unsupported in legacy mode, "
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"try SandyBridge or newer", vdev->vbasedev.name);
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return;
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}
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/*
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* Most of what we're doing here is to enable the ROM to run, so if
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* there's no ROM, there's no point in setting up this quirk.
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* NB. We only seem to get BIOS ROMs, so a UEFI VM would need CSM support.
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*/
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ret = vfio_get_region_info(&vdev->vbasedev,
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VFIO_PCI_ROM_REGION_INDEX, &rom);
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if ((ret || !rom->size) && !vdev->pdev.romfile) {
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error_report("IGD device %s has no ROM, legacy mode disabled",
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vdev->vbasedev.name);
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goto out;
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}
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/*
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* Ignore the hotplug corner case, mark the ROM failed, we can't
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* create the devices we need for legacy mode in the hotplug scenario.
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*/
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if (vdev->pdev.qdev.hotplugged) {
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error_report("IGD device %s hotplugged, ROM disabled, "
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"legacy mode disabled", vdev->vbasedev.name);
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vdev->rom_read_failed = true;
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goto out;
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}
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/*
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* Check whether we have all the vfio device specific regions to
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* support legacy mode (added in Linux v4.6). If not, bail.
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*/
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ret = vfio_get_dev_region_info(&vdev->vbasedev,
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VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL,
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VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, &opregion);
|
|
if (ret) {
|
|
error_report("IGD device %s does not support OpRegion access,"
|
|
"legacy mode disabled", vdev->vbasedev.name);
|
|
goto out;
|
|
}
|
|
|
|
ret = vfio_get_dev_region_info(&vdev->vbasedev,
|
|
VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL,
|
|
VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG, &host);
|
|
if (ret) {
|
|
error_report("IGD device %s does not support host bridge access,"
|
|
"legacy mode disabled", vdev->vbasedev.name);
|
|
goto out;
|
|
}
|
|
|
|
ret = vfio_get_dev_region_info(&vdev->vbasedev,
|
|
VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL,
|
|
VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG, &lpc);
|
|
if (ret) {
|
|
error_report("IGD device %s does not support LPC bridge access,"
|
|
"legacy mode disabled", vdev->vbasedev.name);
|
|
goto out;
|
|
}
|
|
|
|
gmch = vfio_pci_read_config(&vdev->pdev, IGD_GMCH, 4);
|
|
|
|
/*
|
|
* If IGD VGA Disable is clear (expected) and VGA is not already enabled,
|
|
* try to enable it. Probably shouldn't be using legacy mode without VGA,
|
|
* but also no point in us enabling VGA if disabled in hardware.
|
|
*/
|
|
if (!(gmch & 0x2) && !vdev->vga && vfio_populate_vga(vdev, &err)) {
|
|
error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
|
|
error_report("IGD device %s failed to enable VGA access, "
|
|
"legacy mode disabled", vdev->vbasedev.name);
|
|
goto out;
|
|
}
|
|
|
|
/* Create our LPC/ISA bridge */
|
|
ret = vfio_pci_igd_lpc_init(vdev, lpc);
|
|
if (ret) {
|
|
error_report("IGD device %s failed to create LPC bridge, "
|
|
"legacy mode disabled", vdev->vbasedev.name);
|
|
goto out;
|
|
}
|
|
|
|
/* Stuff some host values into the VM PCI host bridge */
|
|
ret = vfio_pci_igd_host_init(vdev, host);
|
|
if (ret) {
|
|
error_report("IGD device %s failed to modify host bridge, "
|
|
"legacy mode disabled", vdev->vbasedev.name);
|
|
goto out;
|
|
}
|
|
|
|
/* Setup OpRegion access */
|
|
ret = vfio_pci_igd_opregion_init(vdev, opregion, &err);
|
|
if (ret) {
|
|
error_append_hint(&err, "IGD legacy mode disabled\n");
|
|
error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
|
|
goto out;
|
|
}
|
|
|
|
/* Setup our quirk to munge GTT addresses to the VM allocated buffer */
|
|
quirk = vfio_quirk_alloc(2);
|
|
igd = quirk->data = g_malloc0(sizeof(*igd));
|
|
igd->vdev = vdev;
|
|
igd->index = ~0;
|
|
igd->bdsm = vfio_pci_read_config(&vdev->pdev, IGD_BDSM, 4);
|
|
igd->bdsm &= ~((1 * MiB) - 1); /* 1MB aligned */
|
|
|
|
memory_region_init_io(&quirk->mem[0], OBJECT(vdev), &vfio_igd_index_quirk,
|
|
igd, "vfio-igd-index-quirk", 4);
|
|
memory_region_add_subregion_overlap(vdev->bars[nr].region.mem,
|
|
0, &quirk->mem[0], 1);
|
|
|
|
memory_region_init_io(&quirk->mem[1], OBJECT(vdev), &vfio_igd_data_quirk,
|
|
igd, "vfio-igd-data-quirk", 4);
|
|
memory_region_add_subregion_overlap(vdev->bars[nr].region.mem,
|
|
4, &quirk->mem[1], 1);
|
|
|
|
QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next);
|
|
|
|
/* Determine the size of stolen memory needed for GTT */
|
|
ggms_mb = (gmch >> (gen < 8 ? 8 : 6)) & 0x3;
|
|
if (gen > 6) {
|
|
ggms_mb = 1 << ggms_mb;
|
|
}
|
|
|
|
/*
|
|
* Assume we have no GMS memory, but allow it to be overrided by device
|
|
* option (experimental). The spec doesn't actually allow zero GMS when
|
|
* when IVD (IGD VGA Disable) is clear, but the claim is that it's unused,
|
|
* so let's not waste VM memory for it.
|
|
*/
|
|
gmch &= ~((gen < 8 ? 0x1f : 0xff) << (gen < 8 ? 3 : 8));
|
|
|
|
if (vdev->igd_gms) {
|
|
if (vdev->igd_gms <= 0x10) {
|
|
gms_mb = vdev->igd_gms * 32;
|
|
gmch |= vdev->igd_gms << (gen < 8 ? 3 : 8);
|
|
} else {
|
|
error_report("Unsupported IGD GMS value 0x%x", vdev->igd_gms);
|
|
vdev->igd_gms = 0;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Request reserved memory for stolen memory via fw_cfg. VM firmware
|
|
* must allocate a 1MB aligned reserved memory region below 4GB with
|
|
* the requested size (in bytes) for use by the Intel PCI class VGA
|
|
* device at VM address 00:02.0. The base address of this reserved
|
|
* memory region must be written to the device BDSM regsiter at PCI
|
|
* config offset 0x5C.
|
|
*/
|
|
bdsm_size = g_malloc(sizeof(*bdsm_size));
|
|
*bdsm_size = cpu_to_le64((ggms_mb + gms_mb) * MiB);
|
|
fw_cfg_add_file(fw_cfg_find(), "etc/igd-bdsm-size",
|
|
bdsm_size, sizeof(*bdsm_size));
|
|
|
|
/* GMCH is read-only, emulated */
|
|
pci_set_long(vdev->pdev.config + IGD_GMCH, gmch);
|
|
pci_set_long(vdev->pdev.wmask + IGD_GMCH, 0);
|
|
pci_set_long(vdev->emulated_config_bits + IGD_GMCH, ~0);
|
|
|
|
/* BDSM is read-write, emulated. The BIOS needs to be able to write it */
|
|
pci_set_long(vdev->pdev.config + IGD_BDSM, 0);
|
|
pci_set_long(vdev->pdev.wmask + IGD_BDSM, ~0);
|
|
pci_set_long(vdev->emulated_config_bits + IGD_BDSM, ~0);
|
|
|
|
/*
|
|
* This IOBAR gives us access to GTTADR, which allows us to write to
|
|
* the GTT itself. So let's go ahead and write zero to all the GTT
|
|
* entries to avoid spurious DMA faults. Be sure I/O access is enabled
|
|
* before talking to the device.
|
|
*/
|
|
if (pread(vdev->vbasedev.fd, &cmd_orig, sizeof(cmd_orig),
|
|
vdev->config_offset + PCI_COMMAND) != sizeof(cmd_orig)) {
|
|
error_report("IGD device %s - failed to read PCI command register",
|
|
vdev->vbasedev.name);
|
|
}
|
|
|
|
cmd = cmd_orig | PCI_COMMAND_IO;
|
|
|
|
if (pwrite(vdev->vbasedev.fd, &cmd, sizeof(cmd),
|
|
vdev->config_offset + PCI_COMMAND) != sizeof(cmd)) {
|
|
error_report("IGD device %s - failed to write PCI command register",
|
|
vdev->vbasedev.name);
|
|
}
|
|
|
|
for (i = 1; i < vfio_igd_gtt_max(vdev); i += 4) {
|
|
vfio_region_write(&vdev->bars[4].region, 0, i, 4);
|
|
vfio_region_write(&vdev->bars[4].region, 4, 0, 4);
|
|
}
|
|
|
|
if (pwrite(vdev->vbasedev.fd, &cmd_orig, sizeof(cmd_orig),
|
|
vdev->config_offset + PCI_COMMAND) != sizeof(cmd_orig)) {
|
|
error_report("IGD device %s - failed to restore PCI command register",
|
|
vdev->vbasedev.name);
|
|
}
|
|
|
|
trace_vfio_pci_igd_bdsm_enabled(vdev->vbasedev.name, ggms_mb + gms_mb);
|
|
|
|
out:
|
|
g_free(rom);
|
|
g_free(opregion);
|
|
g_free(host);
|
|
g_free(lpc);
|
|
}
|