There is no common code between these 2 timer implementation. So it is better to split them. Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net> Message-id: 1368990197-19694-1-git-send-email-jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
466 lines
13 KiB
C
466 lines
13 KiB
C
/*
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* IMX GPT Timer
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*
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* Copyright (c) 2008 OK Labs
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* Copyright (c) 2011 NICTA Pty Ltd
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* Originally written by Hans Jiang
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* Updated by Peter Chubb
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*
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* This code is licensed under GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*
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*/
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#include "hw/hw.h"
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#include "qemu/bitops.h"
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#include "qemu/timer.h"
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#include "hw/ptimer.h"
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#include "hw/sysbus.h"
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#include "hw/arm/imx.h"
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//#define DEBUG_TIMER 1
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#ifdef DEBUG_TIMER
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# define DPRINTF(fmt, args...) \
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do { printf("imx_timer: " fmt , ##args); } while (0)
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#else
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# define DPRINTF(fmt, args...) do {} while (0)
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#endif
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/*
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* Define to 1 for messages about attempts to
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* access unimplemented registers or similar.
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*/
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#define DEBUG_IMPLEMENTATION 1
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#if DEBUG_IMPLEMENTATION
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# define IPRINTF(fmt, args...) \
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do { fprintf(stderr, "imx_timer: " fmt, ##args); } while (0)
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#else
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# define IPRINTF(fmt, args...) do {} while (0)
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#endif
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/*
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* GPT : General purpose timer
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*
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* This timer counts up continuously while it is enabled, resetting itself
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* to 0 when it reaches TIMER_MAX (in freerun mode) or when it
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* reaches the value of ocr1 (in periodic mode). WE simulate this using a
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* QEMU ptimer counting down from ocr1 and reloading from ocr1 in
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* periodic mode, or counting from ocr1 to zero, then TIMER_MAX - ocr1.
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* waiting_rov is set when counting from TIMER_MAX.
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*
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* In the real hardware, there are three comparison registers that can
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* trigger interrupts, and compare channel 1 can be used to
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* force-reset the timer. However, this is a `bare-bones'
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* implementation: only what Linux 3.x uses has been implemented
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* (free-running timer from 0 to OCR1 or TIMER_MAX) .
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*/
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#define TIMER_MAX 0XFFFFFFFFUL
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/* Control register. Not all of these bits have any effect (yet) */
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#define GPT_CR_EN (1 << 0) /* GPT Enable */
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#define GPT_CR_ENMOD (1 << 1) /* GPT Enable Mode */
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#define GPT_CR_DBGEN (1 << 2) /* GPT Debug mode enable */
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#define GPT_CR_WAITEN (1 << 3) /* GPT Wait Mode Enable */
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#define GPT_CR_DOZEN (1 << 4) /* GPT Doze mode enable */
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#define GPT_CR_STOPEN (1 << 5) /* GPT Stop Mode Enable */
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#define GPT_CR_CLKSRC_SHIFT (6)
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#define GPT_CR_CLKSRC_MASK (0x7)
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#define GPT_CR_FRR (1 << 9) /* Freerun or Restart */
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#define GPT_CR_SWR (1 << 15) /* Software Reset */
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#define GPT_CR_IM1 (3 << 16) /* Input capture channel 1 mode (2 bits) */
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#define GPT_CR_IM2 (3 << 18) /* Input capture channel 2 mode (2 bits) */
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#define GPT_CR_OM1 (7 << 20) /* Output Compare Channel 1 Mode (3 bits) */
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#define GPT_CR_OM2 (7 << 23) /* Output Compare Channel 2 Mode (3 bits) */
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#define GPT_CR_OM3 (7 << 26) /* Output Compare Channel 3 Mode (3 bits) */
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#define GPT_CR_FO1 (1 << 29) /* Force Output Compare Channel 1 */
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#define GPT_CR_FO2 (1 << 30) /* Force Output Compare Channel 2 */
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#define GPT_CR_FO3 (1 << 31) /* Force Output Compare Channel 3 */
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#define GPT_SR_OF1 (1 << 0)
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#define GPT_SR_ROV (1 << 5)
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#define GPT_IR_OF1IE (1 << 0)
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#define GPT_IR_ROVIE (1 << 5)
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typedef struct {
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SysBusDevice busdev;
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ptimer_state *timer;
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MemoryRegion iomem;
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DeviceState *ccm;
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uint32_t cr;
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uint32_t pr;
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uint32_t sr;
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uint32_t ir;
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uint32_t ocr1;
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uint32_t ocr2;
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uint32_t ocr3;
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uint32_t icr1;
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uint32_t icr2;
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uint32_t cnt;
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uint32_t waiting_rov;
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qemu_irq irq;
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} IMXTimerGState;
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static const VMStateDescription vmstate_imx_timerg = {
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.name = "imx-timerg",
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.version_id = 2,
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.minimum_version_id = 2,
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.minimum_version_id_old = 2,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(cr, IMXTimerGState),
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VMSTATE_UINT32(pr, IMXTimerGState),
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VMSTATE_UINT32(sr, IMXTimerGState),
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VMSTATE_UINT32(ir, IMXTimerGState),
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VMSTATE_UINT32(ocr1, IMXTimerGState),
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VMSTATE_UINT32(ocr2, IMXTimerGState),
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VMSTATE_UINT32(ocr3, IMXTimerGState),
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VMSTATE_UINT32(icr1, IMXTimerGState),
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VMSTATE_UINT32(icr2, IMXTimerGState),
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VMSTATE_UINT32(cnt, IMXTimerGState),
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VMSTATE_UINT32(waiting_rov, IMXTimerGState),
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VMSTATE_PTIMER(timer, IMXTimerGState),
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VMSTATE_END_OF_LIST()
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}
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};
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static const IMXClk imx_timerg_clocks[] = {
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NOCLK, /* 000 No clock source */
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IPG, /* 001 ipg_clk, 532MHz*/
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IPG, /* 010 ipg_clk_highfreq */
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NOCLK, /* 011 not defined */
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CLK_32k, /* 100 ipg_clk_32k */
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NOCLK, /* 101 not defined */
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NOCLK, /* 110 not defined */
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NOCLK, /* 111 not defined */
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};
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static void imx_timerg_set_freq(IMXTimerGState *s)
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{
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int clksrc;
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uint32_t freq;
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clksrc = (s->cr >> GPT_CR_CLKSRC_SHIFT) & GPT_CR_CLKSRC_MASK;
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freq = imx_clock_frequency(s->ccm, imx_timerg_clocks[clksrc]) / (1 + s->pr);
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DPRINTF("Setting gtimer clksrc %d to frequency %d\n", clksrc, freq);
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if (freq) {
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ptimer_set_freq(s->timer, freq);
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}
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}
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static void imx_timerg_update(IMXTimerGState *s)
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{
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uint32_t flags = s->sr & s->ir & (GPT_SR_OF1 | GPT_SR_ROV);
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DPRINTF("g-timer SR: %s %s IR=%s %s, %s\n",
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s->sr & GPT_SR_OF1 ? "OF1" : "",
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s->sr & GPT_SR_ROV ? "ROV" : "",
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s->ir & GPT_SR_OF1 ? "OF1" : "",
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s->ir & GPT_SR_ROV ? "ROV" : "",
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s->cr & GPT_CR_EN ? "CR_EN" : "Not Enabled");
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qemu_set_irq(s->irq, (s->cr & GPT_CR_EN) && flags);
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}
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static uint32_t imx_timerg_update_counts(IMXTimerGState *s)
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{
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uint64_t target = s->waiting_rov ? TIMER_MAX : s->ocr1;
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uint64_t cnt = ptimer_get_count(s->timer);
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s->cnt = target - cnt;
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return s->cnt;
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}
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static void imx_timerg_reload(IMXTimerGState *s, uint32_t timeout)
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{
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uint64_t diff_cnt;
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if (!(s->cr & GPT_CR_FRR)) {
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IPRINTF("IMX_timerg_reload --- called in reset-mode\n");
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return;
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}
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/*
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* For small timeouts, qemu sometimes runs too slow.
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* Better deliver a late interrupt than none.
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*
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* In Reset mode (FRR bit clear)
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* the ptimer reloads itself from OCR1;
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* in free-running mode we need to fake
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* running from 0 to ocr1 to TIMER_MAX
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*/
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if (timeout > s->cnt) {
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diff_cnt = timeout - s->cnt;
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} else {
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diff_cnt = 0;
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}
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ptimer_set_count(s->timer, diff_cnt);
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}
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static uint64_t imx_timerg_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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IMXTimerGState *s = (IMXTimerGState *)opaque;
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DPRINTF("g-read(offset=%x)", (unsigned int)(offset >> 2));
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switch (offset >> 2) {
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case 0: /* Control Register */
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DPRINTF(" cr = %x\n", s->cr);
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return s->cr;
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case 1: /* prescaler */
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DPRINTF(" pr = %x\n", s->pr);
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return s->pr;
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case 2: /* Status Register */
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DPRINTF(" sr = %x\n", s->sr);
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return s->sr;
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case 3: /* Interrupt Register */
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DPRINTF(" ir = %x\n", s->ir);
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return s->ir;
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case 4: /* Output Compare Register 1 */
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DPRINTF(" ocr1 = %x\n", s->ocr1);
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return s->ocr1;
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case 5: /* Output Compare Register 2 */
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DPRINTF(" ocr2 = %x\n", s->ocr2);
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return s->ocr2;
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case 6: /* Output Compare Register 3 */
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DPRINTF(" ocr3 = %x\n", s->ocr3);
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return s->ocr3;
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case 7: /* input Capture Register 1 */
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DPRINTF(" icr1 = %x\n", s->icr1);
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return s->icr1;
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case 8: /* input Capture Register 2 */
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DPRINTF(" icr2 = %x\n", s->icr2);
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return s->icr2;
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case 9: /* cnt */
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imx_timerg_update_counts(s);
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DPRINTF(" cnt = %x\n", s->cnt);
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return s->cnt;
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}
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IPRINTF("imx_timerg_read: Bad offset %x\n",
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(int)offset >> 2);
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return 0;
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}
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static void imx_timerg_reset(DeviceState *dev)
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{
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IMXTimerGState *s = container_of(dev, IMXTimerGState, busdev.qdev);
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/*
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* Soft reset doesn't touch some bits; hard reset clears them
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*/
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s->cr &= ~(GPT_CR_EN|GPT_CR_ENMOD|GPT_CR_STOPEN|GPT_CR_DOZEN|
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GPT_CR_WAITEN|GPT_CR_DBGEN);
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s->sr = 0;
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s->pr = 0;
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s->ir = 0;
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s->cnt = 0;
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s->ocr1 = TIMER_MAX;
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s->ocr2 = TIMER_MAX;
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s->ocr3 = TIMER_MAX;
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s->icr1 = 0;
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s->icr2 = 0;
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ptimer_stop(s->timer);
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ptimer_set_limit(s->timer, TIMER_MAX, 1);
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ptimer_set_count(s->timer, TIMER_MAX);
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imx_timerg_set_freq(s);
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}
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static void imx_timerg_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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IMXTimerGState *s = (IMXTimerGState *)opaque;
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DPRINTF("g-write(offset=%x, value = 0x%x)\n", (unsigned int)offset >> 2,
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(unsigned int)value);
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switch (offset >> 2) {
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case 0: {
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uint32_t oldcr = s->cr;
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/* CR */
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if (value & GPT_CR_SWR) { /* force reset */
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value &= ~GPT_CR_SWR;
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imx_timerg_reset(&s->busdev.qdev);
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imx_timerg_update(s);
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}
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s->cr = value & ~0x7c00;
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imx_timerg_set_freq(s);
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if ((oldcr ^ value) & GPT_CR_EN) {
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if (value & GPT_CR_EN) {
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if (value & GPT_CR_ENMOD) {
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ptimer_set_count(s->timer, s->ocr1);
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s->cnt = 0;
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}
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ptimer_run(s->timer,
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(value & GPT_CR_FRR) && (s->ocr1 != TIMER_MAX));
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} else {
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ptimer_stop(s->timer);
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};
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}
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return;
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}
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case 1: /* Prescaler */
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s->pr = value & 0xfff;
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imx_timerg_set_freq(s);
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return;
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case 2: /* SR */
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/*
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* No point in implementing the status register bits to do with
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* external interrupt sources.
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*/
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value &= GPT_SR_OF1 | GPT_SR_ROV;
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s->sr &= ~value;
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imx_timerg_update(s);
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return;
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case 3: /* IR -- interrupt register */
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s->ir = value & 0x3f;
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imx_timerg_update(s);
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return;
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case 4: /* OCR1 -- output compare register */
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/* In non-freerun mode, reset count when this register is written */
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if (!(s->cr & GPT_CR_FRR)) {
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s->waiting_rov = 0;
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ptimer_set_limit(s->timer, value, 1);
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} else {
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imx_timerg_update_counts(s);
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if (value > s->cnt) {
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s->waiting_rov = 0;
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imx_timerg_reload(s, value);
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} else {
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s->waiting_rov = 1;
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imx_timerg_reload(s, TIMER_MAX - s->cnt);
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}
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}
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s->ocr1 = value;
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return;
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case 5: /* OCR2 -- output compare register */
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case 6: /* OCR3 -- output compare register */
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default:
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IPRINTF("imx_timerg_write: Bad offset %x\n",
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(int)offset >> 2);
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}
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}
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static void imx_timerg_timeout(void *opaque)
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{
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IMXTimerGState *s = (IMXTimerGState *)opaque;
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DPRINTF("imx_timerg_timeout, waiting rov=%d\n", s->waiting_rov);
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if (s->cr & GPT_CR_FRR) {
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/*
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* Free running timer from 0 -> TIMERMAX
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* Generates interrupt at TIMER_MAX and at cnt==ocr1
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* If ocr1 == TIMER_MAX, then no need to reload timer.
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*/
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if (s->ocr1 == TIMER_MAX) {
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DPRINTF("s->ocr1 == TIMER_MAX, FRR\n");
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s->sr |= GPT_SR_OF1 | GPT_SR_ROV;
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imx_timerg_update(s);
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return;
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}
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if (s->waiting_rov) {
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/*
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* We were waiting for cnt==TIMER_MAX
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*/
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s->sr |= GPT_SR_ROV;
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s->waiting_rov = 0;
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s->cnt = 0;
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imx_timerg_reload(s, s->ocr1);
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} else {
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/* Must have got a cnt==ocr1 timeout. */
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s->sr |= GPT_SR_OF1;
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s->cnt = s->ocr1;
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s->waiting_rov = 1;
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imx_timerg_reload(s, TIMER_MAX);
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}
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imx_timerg_update(s);
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return;
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}
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s->sr |= GPT_SR_OF1;
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imx_timerg_update(s);
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}
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static const MemoryRegionOps imx_timerg_ops = {
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.read = imx_timerg_read,
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.write = imx_timerg_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static int imx_timerg_init(SysBusDevice *dev)
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{
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IMXTimerGState *s = FROM_SYSBUS(IMXTimerGState, dev);
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QEMUBH *bh;
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sysbus_init_irq(dev, &s->irq);
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memory_region_init_io(&s->iomem, &imx_timerg_ops,
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s, "imxg-timer",
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0x00001000);
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sysbus_init_mmio(dev, &s->iomem);
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bh = qemu_bh_new(imx_timerg_timeout, s);
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s->timer = ptimer_init(bh);
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/* Hard reset resets extra bits in CR */
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s->cr = 0;
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return 0;
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}
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void imx_timerg_create(const hwaddr addr,
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qemu_irq irq,
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DeviceState *ccm)
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{
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IMXTimerGState *pp;
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DeviceState *dev;
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dev = sysbus_create_simple("imx_timerg", addr, irq);
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pp = container_of(dev, IMXTimerGState, busdev.qdev);
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pp->ccm = ccm;
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}
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static void imx_timerg_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = imx_timerg_init;
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dc->vmsd = &vmstate_imx_timerg;
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dc->reset = imx_timerg_reset;
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dc->desc = "i.MX general timer";
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}
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static const TypeInfo imx_timerg_info = {
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.name = "imx_timerg",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IMXTimerGState),
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.class_init = imx_timerg_class_init,
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};
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static void imx_timer_register_types(void)
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{
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type_register_static(&imx_timerg_info);
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}
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type_init(imx_timer_register_types)
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