ec150c7e09
Back in 2016, we discussed[1] rules for headers, and these were
generally liked:
1. Have a carefully curated header that's included everywhere first. We
got that already thanks to Peter: osdep.h.
2. Headers should normally include everything they need beyond osdep.h.
If exceptions are needed for some reason, they must be documented in
the header. If all that's needed from a header is typedefs, put
those into qemu/typedefs.h instead of including the header.
3. Cyclic inclusion is forbidden.
This patch gets include/ closer to obeying 2.
It's actually extracted from my "[RFC] Baby steps towards saner
headers" series[2], which demonstrates a possible path towards
checking 2 automatically. It passes the RFC test there.
[1] Message-ID: <87h9g8j57d.fsf@blackfin.pond.sub.org>
https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html
[2] Message-Id: <20190711122827.18970-1-armbru@redhat.com>
https://lists.nongnu.org/archive/html/qemu-devel/2019-07/msg02715.html
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20190812052359.30071-2-armbru@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
43 lines
1.1 KiB
C
43 lines
1.1 KiB
C
#ifndef ALLWINNER_A10_PIC_H
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#define ALLWINNER_A10_PIC_H
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#include "hw/sysbus.h"
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#define TYPE_AW_A10_PIC "allwinner-a10-pic"
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#define AW_A10_PIC(obj) OBJECT_CHECK(AwA10PICState, (obj), TYPE_AW_A10_PIC)
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#define AW_A10_PIC_VECTOR 0
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#define AW_A10_PIC_BASE_ADDR 4
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#define AW_A10_PIC_PROTECT 8
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#define AW_A10_PIC_NMI 0xc
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#define AW_A10_PIC_IRQ_PENDING 0x10
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#define AW_A10_PIC_FIQ_PENDING 0x20
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#define AW_A10_PIC_SELECT 0x30
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#define AW_A10_PIC_ENABLE 0x40
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#define AW_A10_PIC_MASK 0x50
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#define AW_A10_PIC_INT_NR 95
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#define AW_A10_PIC_REG_NUM DIV_ROUND_UP(AW_A10_PIC_INT_NR, 32)
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typedef struct AwA10PICState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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qemu_irq parent_fiq;
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qemu_irq parent_irq;
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uint32_t vector;
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uint32_t base_addr;
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uint32_t protect;
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uint32_t nmi;
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uint32_t irq_pending[AW_A10_PIC_REG_NUM];
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uint32_t fiq_pending[AW_A10_PIC_REG_NUM];
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uint32_t select[AW_A10_PIC_REG_NUM];
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uint32_t enable[AW_A10_PIC_REG_NUM];
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uint32_t mask[AW_A10_PIC_REG_NUM];
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/*priority setting here*/
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} AwA10PICState;
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#endif
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